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mips: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:21:19 +00:00
parent e91d4ae878
commit f1ffd05af1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=365076
140 changed files with 61 additions and 357 deletions
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2
sys/mips/atheros/apb.c
View File

@ -356,7 +356,6 @@ apb_filter(void *arg)
reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS);
for (irq = 0; irq < APB_NIRQS; irq++) {
if (reg & (1 << irq)) {
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
@ -509,7 +508,6 @@ apb_print_child(device_t bus, device_t child)
return (retval);
}
static device_method_t apb_methods[] = {
DEVMETHOD(bus_activate_resource, apb_activate_resource),
DEVMETHOD(bus_add_child, apb_add_child),

5
sys/mips/atheros/ar531x/apb.c
View File

@ -386,7 +386,6 @@ apb_release_resource(device_t dev, device_t child, int type,
return (0);
}
static int
apb_setup_intr(device_t bus, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *handler,
@ -402,7 +401,7 @@ apb_setup_intr(device_t bus, device_t child, struct resource *ires,
#ifdef INTRNG
struct intr_irqsrc *isrc;
const char *name;
if ((rman_get_flags(ires) & RF_SHAREABLE) == 0)
flags |= INTR_EXCL;
@ -479,7 +478,6 @@ apb_teardown_intr(device_t dev, device_t child, struct resource *ires,
#endif
}
static int
apb_filter(void *arg)
{
@ -496,7 +494,6 @@ apb_filter(void *arg)
for (irq = 0; irq < APB_NIRQS; irq++) {
if (reg & (1 << irq)) {
if(ar531x_soc >= AR531X_SOC_AR5315) {
ATH_WRITE_REG(AR5315_SYSREG_BASE +
AR5315_SYSREG_MISC_INTSTAT,

1
sys/mips/atheros/ar531x/ar5312_chip.c
View File

@ -87,7 +87,6 @@ ar5312_chip_detect_sys_frequency(void)
uint32_t predivisor;
uint32_t multiplier;
const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL);
if(ar531x_soc == AR531X_SOC_AR5313) {
predivisor = __SHIFTOUT(clockctl, AR2313_CLOCKCTL_PREDIVIDE);

2
sys/mips/atheros/ar531x/ar5315_chip.c
View File

@ -181,7 +181,7 @@ ar5315_chip_device_start(void)
ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL,
ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) |
AR5315_ARB_ENET);
// set Ethernet controller byteswap control
/*
ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN,

4
sys/mips/atheros/ar531x/ar5315_cpudef.h
View File

@ -122,18 +122,14 @@ extern uint32_t u_ar531x_gpio_pins;
extern uint32_t u_ar531x_wdog_ctl;
extern uint32_t u_ar531x_wdog_timer;
static inline uint32_t ar531x_cpu_freq(void) { return u_ar531x_cpu_freq; }
static inline uint32_t ar531x_ahb_freq(void) { return u_ar531x_ahb_freq; }
static inline uint32_t ar531x_ddr_freq(void) { return u_ar531x_ddr_freq; }
static inline uint32_t ar531x_uart_addr(void) { return u_ar531x_uart_addr; }
static inline uint32_t ar531x_gpio_di(void) { return u_ar531x_gpio_di; }
static inline uint32_t ar531x_gpio_cr(void) { return u_ar531x_gpio_cr; }
static inline uint32_t ar531x_gpio_do(void) { return u_ar531x_gpio_do; }
static inline uint32_t ar531x_gpio_pins(void) { return u_ar531x_gpio_pins; }
static inline uint32_t ar531x_wdog_ctl(void) { return u_ar531x_wdog_ctl; }
static inline uint32_t ar531x_wdog_timer(void) { return u_ar531x_wdog_timer; }
#endif

2
sys/mips/atheros/ar531x/ar5315_gpio.c
View File

@ -308,8 +308,6 @@ ar5315_gpio_filter(void *arg)
return (FILTER_STRAY);
}
static void
ar5315_gpio_intr(void *arg)
{

1
sys/mips/atheros/ar531x/ar5315_machdep.c
View File

@ -241,7 +241,6 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused,
/* Detect the system type - this is needed for subsequent chipset-specific calls */
ar531x_device_soc_init();
ar531x_detect_sys_frequency();

9
sys/mips/atheros/ar531x/ar5315_setup.c
View File

@ -39,12 +39,12 @@ __FBSDID("$FreeBSD$");
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <net/ethernet.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
@ -52,7 +52,7 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/atheros/ar531x/ar5315reg.h>
#include <mips/atheros/ar531x/ar5312reg.h>
#include <mips/atheros/ar531x/ar5315_setup.h>
@ -158,4 +158,3 @@ ar5315_get_system_type(void)
{
return ar5315_sys_type;
}

3
sys/mips/atheros/ar531x/ar5315_wdog.c
View File

@ -116,12 +116,11 @@ ar5315_wdog_sysctl(device_t dev)
"whether the system rebooted from the watchdog");
}
static int
ar5315_wdog_attach(device_t dev)
{
struct ar5315_wdog_softc *sc = device_get_softc(dev);
/* Initialise */
sc->reboot_from_watchdog = 0;
sc->armed = 0;

2
sys/mips/atheros/ar531x/ar5315reg.h
View File

@ -223,7 +223,7 @@
#define ATH_READ_REG(reg) \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
#define ATH_WRITE_REG(reg, val) \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)

4
sys/mips/atheros/ar531x/if_are.c
View File

@ -195,7 +195,6 @@ DRIVER_MODULE(aremdio, nexus, aremdio_driver, aremdio_devclass, 0, 0);
DRIVER_MODULE(mdio, aremdio, mdio_driver, mdio_devclass, 0, 0);
#endif
static int
are_probe(device_t dev)
{
@ -1472,7 +1471,6 @@ are_fixup_rx(struct mbuf *m)
m->m_data -= ETHER_ALIGN;
}
static void
are_tx(struct are_softc *sc)
{
@ -1538,7 +1536,6 @@ are_tx(struct are_softc *sc)
sc->are_cdata.are_tx_ring_map, BUS_DMASYNC_PREWRITE);
}
static void
are_rx(struct are_softc *sc)
{
@ -1611,7 +1608,6 @@ are_rx(struct are_softc *sc)
bus_dmamap_sync(sc->are_cdata.are_rx_ring_tag,
sc->are_cdata.are_rx_ring_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
}
if (prog > 0) {

5
sys/mips/atheros/ar531x/if_arereg.h
View File

@ -141,7 +141,6 @@ struct are_softc {
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->are_btag, sc->are_bhandle, reg)
/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */
/*-
@ -254,7 +253,7 @@ struct are_softc {
#define CSR_MIIDATA 0x0018 /* mii data */
#define CSR_FLOWC 0x001C /* flow control */
#define CSR_VL1 0x0020 /* vlan 1 tag */
/* these are more or less normal Tulip registers */
#define CSR_BUSMODE 0x1000 /* bus mode */
#define CSR_TXPOLL 0x1004 /* tx poll demand */
@ -331,7 +330,6 @@ struct are_softc {
/* CSR_TXPOLL - Transmit Poll Demand */
#define TXPOLL_TPD 0x00000001 /* transmit poll demand */
/* CSR_RXPOLL - Receive Poll Demand */
#define RXPOLL_RPD 0x00000001 /* receive poll demand */
@ -393,7 +391,6 @@ struct are_softc {
/* CSR_INTEN - Interrupt Enable */
/* See bits for CSR_STATUS -- Status */
/* CSR_MISSED - Missed Frames */
#define MISSED_MFC 0xffff0000 /* missed packet count */
#define MISSED_FOC 0x0000ffff /* fifo overflow counter */

1
sys/mips/atheros/ar71xx_cpudef.h
View File

@ -171,7 +171,6 @@ extern uint32_t u_ar71xx_ddr_freq;
extern uint32_t u_ar71xx_uart_freq;
extern uint32_t u_ar71xx_wdt_freq;
extern uint32_t u_ar71xx_mdio_freq;
static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }

2
sys/mips/atheros/ar71xx_gpio.c
View File

@ -411,8 +411,6 @@ ar71xx_gpio_filter(void *arg)
return (FILTER_STRAY);
}
static void
ar71xx_gpio_intr(void *arg)
{

1
sys/mips/atheros/ar71xx_ohci.c
View File

@ -79,7 +79,6 @@ ar71xx_ohci_intr(void *arg)
ohci_interrupt(arg);
}
static int
ar71xx_ohci_attach(device_t dev)
{

3
sys/mips/atheros/ar71xx_pci.c
View File

@ -358,7 +358,6 @@ ar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func)
return;
}
device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n",
flash_addr, bus, slot, func);
ar71xx_pci_fixup(dev, bus, slot, func, flash_addr, size);
@ -660,7 +659,7 @@ static int
ar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin)
{
struct ar71xx_pci_softc *sc = device_get_softc(pcib);
if (pci_get_slot(device) < sc->sc_baseslot)
panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT",
__func__, pci_get_slot(device));

2
sys/mips/atheros/ar71xx_pci_bus_space.c
View File

@ -188,7 +188,7 @@ pcimem_bs_w_2_s(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
static uint32_t
pcimem_bs_r_4_s(void *t, bus_space_handle_t h, bus_size_t o)
{
return le32toh(readl(h + o));
}

9
sys/mips/atheros/ar71xx_setup.c
View File

@ -39,12 +39,12 @@ __FBSDID("$FreeBSD$");
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <net/ethernet.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
@ -52,7 +52,7 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar933xreg.h>
#include <mips/atheros/ar934xreg.h>
@ -234,4 +234,3 @@ ar71xx_get_system_type(void)
{
return ar71xx_sys_type;
}

1
sys/mips/atheros/ar71xx_spi.c
View File

@ -282,7 +282,6 @@ static device_method_t ar71xx_spi_methods[] = {
DEVMETHOD(device_detach, ar71xx_spi_detach),
DEVMETHOD(spibus_transfer, ar71xx_spi_transfer),
{0, 0}
};

3
sys/mips/atheros/ar71xx_wdog.c
View File

@ -143,12 +143,11 @@ ar71xx_wdog_sysctl(device_t dev)
"whether the system rebooted from the watchdog");
}
static int
ar71xx_wdog_attach(device_t dev)
{
struct ar71xx_wdog_softc *sc = device_get_softc(dev);
/* Initialise */
sc->reboot_from_watchdog = 0;
sc->armed = 0;

2
sys/mips/atheros/ar724x_pci.c
View File

@ -594,7 +594,6 @@ ar724x_pci_intr(void *arg)
struct intr_event *event;
uint32_t reg, irq, mask;
reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
/*
@ -602,7 +601,6 @@ ar724x_pci_intr(void *arg)
*/
reg &= mask;
if (reg & AR724X_PCI_INTR_DEV0) {
irq = AR71XX_PCI_IRQ_START;
event = sc->sc_eventstab[irq];
if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {

1
sys/mips/atheros/ar933x_chip.c
View File

@ -215,7 +215,6 @@ ar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
}
}
static uint32_t
ar933x_chip_get_eth_pll(unsigned int mac, int speed)
{

1
sys/mips/atheros/ar934x_chip.c
View File

@ -286,7 +286,6 @@ ar934x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
}
}
static uint32_t
ar934x_chip_get_eth_pll(unsigned int mac, int speed)
{

11
sys/mips/atheros/if_arge.c
View File

@ -84,7 +84,6 @@ __FBSDID("$FreeBSD$");
#include "mdio_if.h"
#endif
MODULE_DEPEND(arge, ether, 1, 1, 1);
MODULE_DEPEND(arge, miibus, 1, 1, 1);
MODULE_VERSION(arge, 1);
@ -230,7 +229,7 @@ static device_method_t argemdio_methods[] = {
/* bus interface */
DEVMETHOD(bus_add_child, device_add_child_ordered),
/* MDIO access */
DEVMETHOD(mdio_readreg, arge_miibus_readreg),
DEVMETHOD(mdio_writereg, arge_miibus_writereg),
@ -1242,7 +1241,6 @@ arge_update_link_locked(struct arge_softc *sc)
}
if (mii->mii_media_status & IFM_ACTIVE) {
media = IFM_SUBTYPE(mii->mii_media_active);
if (media != IFM_NONE) {
sc->arge_link_status = 1;
@ -1373,7 +1371,6 @@ arge_set_pll(struct arge_softc *sc, int media, int duplex)
#endif
}
static void
arge_reset_dma(struct arge_softc *sc)
{
@ -1738,7 +1735,6 @@ arge_start_locked(struct ifnet *ifp)
if (m_head == NULL)
break;
/*
* Pack the data into the transmit ring.
*/
@ -1784,7 +1780,6 @@ arge_stop(struct arge_softc *sc)
arge_tx_ring_free(sc);
}
static int
arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
{
@ -2419,7 +2414,6 @@ arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
}
#endif /* DEVICE_POLLING */
static void
arge_tx_locked(struct arge_softc *sc)
{
@ -2484,7 +2478,6 @@ arge_tx_locked(struct arge_softc *sc)
sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
}
static int
arge_rx_locked(struct arge_softc *sc)
{
@ -2541,7 +2534,6 @@ arge_rx_locked(struct arge_softc *sc)
}
if (prog > 0) {
i = sc->arge_cdata.arge_rx_cons;
for (; prog > 0 ; prog--) {
if (arge_newbuf(sc, i) != 0) {
@ -2699,7 +2691,6 @@ arge_intr(void *arg)
ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
}
static void
arge_tick(void *xsc)
{

1
sys/mips/atheros/if_argevar.h
View File

@ -50,7 +50,6 @@
((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
#define ARGE_INC(x,y) (x) = (((x) + 1) % y)
#define ARGE_MII_TIMEOUT 1000
#define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx)

1
sys/mips/atheros/pcf2123reg.h
View File

@ -66,4 +66,3 @@
#define PCF2123_WRITE(reg) (PCF2123_CMD_WRITE | (1 << 4) | (reg))
#endif /* __PCF2123REG_H__ */

1
sys/mips/atheros/qca955xreg.h
View File

@ -193,7 +193,6 @@
#define QCA955X_NFC_BASE 0x1b800200
#define QCA955X_NFC_SIZE 0xb8
/* GMAC Interface */
#define QCA955X_GMAC_REG_ETH_CFG (QCA955X_GMAC_BASE + 0x00)

4
sys/mips/atheros/uart_dev_ar933x.c
View File

@ -54,8 +54,6 @@ __FBSDID("$FreeBSD$");
#define ar933x_setreg(bas, reg, value) \
bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
static int
ar933x_drain(struct uart_bas *bas, int what)
{
@ -78,7 +76,6 @@ ar933x_drain(struct uart_bas *bas, int what)
if (what & UART_DRAIN_RECEIVER) {
limit=10*4096;
while (--limit) {
/* XXX duplicated from ar933x_getc() */
/* XXX TODO: refactor! */
@ -193,7 +190,6 @@ ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
return (0);
}
/*
* Low-level UART interface.
*/

2
sys/mips/beri/beri_iommu.c
View File

@ -210,7 +210,6 @@ beri_iommu_detach(device_t dev)
}
static device_method_t beri_iommu_methods[] = {
/* xDMA IOMMU interface */
DEVMETHOD(xdma_iommu_init, beri_iommu_init),
DEVMETHOD(xdma_iommu_release, beri_iommu_release),
@ -221,7 +220,6 @@ static device_method_t beri_iommu_methods[] = {
DEVMETHOD(device_probe, beri_iommu_probe),
DEVMETHOD(device_attach, beri_iommu_attach),
DEVMETHOD(device_detach, beri_iommu_detach),
{ 0, 0 }
};

1
sys/mips/beri/beri_machdep.c
View File

@ -115,7 +115,6 @@ mips_init(void)
#ifdef FDT
if (fdt_get_mem_regions(mr, &mr_cnt, &val) == 0) {
physmem = btoc(val);
KASSERT((phys_avail[0] >= mr[0].mr_start) && \

1
sys/mips/beri/beri_mp.c
View File

@ -171,7 +171,6 @@ platform_init_secondary(int cpuid)
}
}
void
platform_ipi_send(int cpuid)
{

1
sys/mips/broadcom/bcm_bmips.c
View File

@ -103,7 +103,6 @@ bcm_bmips_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
static int
bcm_bmips_attach(device_t dev)
{

1
sys/mips/broadcom/bcm_bmips_exts.h
View File

@ -39,7 +39,6 @@
* $FreeBSD$
*/
/* *********************************************************************
* Broadcom Common Firmware Environment (CFE)
*

1
sys/mips/broadcom/bcm_mips.c
View File

@ -477,7 +477,6 @@ bcm_mips_pic_teardown_intr(device_t dev, struct intr_irqsrc *irqsrc,
return (error);
}
/** return our PIC's xref */
static uintptr_t
bcm_mips_pic_xref(struct bcm_mips_softc *sc)

1
sys/mips/broadcom/bcm_mips74k.c
View File

@ -200,7 +200,6 @@ bcm_mips74k_detach(device_t dev)
return (0);
}
/* PIC_DISABLE_INTR() */
static void
bcm_mips74k_pic_disable_intr(device_t dev, struct intr_irqsrc *irqsrc)

1
sys/mips/broadcom/bcm_mips74kreg.h
View File

@ -64,5 +64,4 @@
#define BCM_MIPS74K_GET_TIMER_IRQ() \
((mips_rd_intctl() & MIPS_INTCTL_IPTI_MASK) >> MIPS_INTCTL_IPTI_SHIFT)
#endif /* _MIPS_BROADCOM_MIPS74KREG_H_ */

2
sys/mips/broadcom/bcm_mipsvar.h
View File

@ -51,7 +51,6 @@ struct bcm_mips_softc;
#define BCM_MIPS_IRQ_SHARED 0 /**< MIPS CPU IRQ reserved for shared interrupt handling */
#define INTR_MAP_DATA_BCM_MIPS INTR_MAP_DATA_PLAT_2 /**< Broadcom MIPS PIC interrupt map data type */
int bcm_mips_attach(device_t dev, u_int num_cpuirqs, u_int timer_irq,
driver_filter_t filter);
int bcm_mips_detach(device_t dev);
@ -100,7 +99,6 @@ struct bcm_mips_softc {
struct mtx mtx;
};
#define BCM_MIPS_IVEC_MASK(_isrc) (1 << ((_isrc)->ivec))
#define BCM_MIPS_LOCK_INIT(sc) \

5
sys/mips/broadcom/bcm_nvram_cfe.c
View File

@ -104,7 +104,6 @@ bhnd_nvram_cfe_probe(device_t dev)
return (BUS_PROBE_NOWILDCARD);
}
static int
bhnd_nvram_cfe_attach(device_t dev)
{
@ -240,7 +239,6 @@ bcm_nvram_find_cfedev(struct bcm_nvram_iocfe *iocfe,
return (ENODEV);
}
/**
* Initialize a new CFE device-backed I/O context.
*
@ -343,7 +341,6 @@ bcm_nvram_iocfe_init(struct bcm_nvram_iocfe *iocfe, char *dname)
req_blk_erase = !(fi.flash_flags & FLASH_FLAG_NOERASE);
}
/* Verify that the full NVRAM layout can be represented via size_t */
if (nv_size > SIZE_MAX || SIZE_MAX - nv_size < nv_offset) {
IOCFE_LOG(iocfe, "invalid NVRAM layout (%#x/%#jx)\n",
@ -449,7 +446,7 @@ bhnd_nvram_iocfe_read(struct bhnd_nvram_io *io, size_t offset, void *buffer,
cfe_noff = cfe_offset + nread;
p = ((uint8_t *)buffer + nread);
nreq = ummin(INT_MAX, remain);
nr = cfe_readblk(iocfe->fd, cfe_noff, p, nreq);
if (nr < 0) {
IOCFE_LOG(iocfe, "cfe_readblk() failed: %d\n", nr);

7
sys/mips/broadcom/bcm_pmu.c
View File

@ -121,7 +121,7 @@ bcm_get_uart_clkcfg(struct bcm_platform *bp)
/* PLL M2 clock source? */
if (!bcm_has_pmu(bp) && BCM_PMU_PLL_TYPE(bp) == CHIPC_PLL_TYPE1) {
uint32_t n, m;
n = BCM_CHIPC_READ_4(bp, CHIPC_CLKC_N);
m = BCM_CHIPC_READ_4(bp, CHIPC_CLKC_M2);
@ -130,7 +130,7 @@ bcm_get_uart_clkcfg(struct bcm_platform *bp)
BCM_UART_RCLK_PLL_T1_DIV,
bhnd_pwrctl_clock_rate(BCM_PMU_PLL_TYPE(bp), n, m)
};
return (cfg);
}
@ -247,7 +247,7 @@ bcm_get_cpufreq(struct bcm_platform *bp)
m = BCM_CHIPC_READ_4(bp, mreg);
return (bhnd_pwrctl_cpu_clock_rate(&bp->cid, pll_type, n, m));
}
/** Backplane clock frequency (in Hz) */
@ -277,7 +277,6 @@ bcm_get_sifreq(struct bcm_platform *bp)
return (bhnd_pwrctl_si_clock_rate(&bp->cid, pll_type, n, m));
}
static uint32_t
bcm_pmu_read4(bus_size_t reg, void *ctx) {
struct bcm_platform *bp = ctx;

1
sys/mips/broadcom/bhnd_nexus.c
View File

@ -63,7 +63,6 @@ __FBSDID("$FreeBSD$");
#include "bhnd_nexusvar.h"
/**
* Default bhnd_nexus implementation of BHND_BUS_GET_SERVICE_REGISTRY().
*/

1
sys/mips/broadcom/uart_bus_chipc.c
View File

@ -50,7 +50,6 @@ __FBSDID("$FreeBSD$");
#include "bcm_machdep.h"
static int
uart_chipc_probe(device_t dev)
{

9
sys/mips/cavium/ciu.c
View File

@ -143,7 +143,7 @@ ciu_attach(device_t dev)
sc->irq_rman.rm_type = RMAN_ARRAY;
sc->irq_rman.rm_descr = "CIU IRQ";
error = rman_init(&sc->irq_rman);
if (error != 0)
return (error);
@ -178,7 +178,7 @@ ciu_alloc_resource(device_t bus, device_t child, int type, int *rid,
{
struct resource *res;
struct ciu_softc *sc;
sc = device_get_softc(bus);
switch (type) {
@ -276,7 +276,7 @@ ciu_bind_intr(device_t bus, device_t child, struct resource *res, int cpu)
{
struct intr_event *event;
int irq;
irq = rman_get_start(res);
if (irq <= CIU_IRQ_EN0_END)
event = ciu_en0_intr_events[irq - CIU_IRQ_EN0_BEGIN];
@ -295,7 +295,7 @@ ciu_describe_intr(device_t bus, device_t child, struct resource *res,
mips_intrcnt_t intrcnt;
int error;
int irq;
irq = rman_get_start(res);
if (irq <= CIU_IRQ_EN0_END) {
event = ciu_en0_intr_events[irq - CIU_IRQ_EN0_BEGIN];
@ -476,7 +476,6 @@ static device_method_t ciu_methods[] = {
DEVMETHOD(bus_add_child, bus_generic_add_child),
DEVMETHOD(bus_hinted_child, ciu_hinted_child),
{ 0, 0 }
};

2
sys/mips/cavium/cryptocteon/cavium_crypto.c
View File

@ -388,7 +388,6 @@ octo_aes_cbc_encrypt(
return 0;
}
int
octo_aes_cbc_decrypt(
struct octo_sess *od,
@ -646,7 +645,6 @@ octo_aes_cbc_sha1_encrypt(
IOV_CONSUME(iov, data32, data_i, data_l);
mydata[1].data32[1] = *data32;
if (crypt_off <= 0) {
if (crypt_len > 0) {
CVMX_MT_AES_ENC_CBC0(*pdata);

3
sys/mips/cavium/cryptocteon/cryptocteon.c
View File

@ -372,7 +372,6 @@ cryptocteon_process(device_t dev, struct cryptop *crp, int hint)
panic("can't happen");
}
/*
* setup a new explicit key
*/
@ -381,7 +380,6 @@ cryptocteon_process(device_t dev, struct cryptop *crp, int hint)
if (crp->crp_auth_key != NULL)
cryptocteon_calc_hash(csp, crp->crp_auth_key, od);
if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
(*od->octo_encrypt)(od, od->octo_iov, iovcnt, iovlen,
auth_off, auth_len, crypt_off, crypt_len, icv, ivp);
@ -414,7 +412,6 @@ static device_method_t cryptocteon_methods[] = {
DEVMETHOD(cryptodev_probesession, cryptocteon_probesession),
DEVMETHOD(cryptodev_newsession, cryptocteon_newsession),
DEVMETHOD(cryptodev_process, cryptocteon_process),
{ 0, 0 }
};

6
sys/mips/cavium/if_octm.c
View File

@ -99,7 +99,6 @@ static device_method_t octm_methods[] = {
DEVMETHOD(device_attach, octm_attach),
DEVMETHOD(device_detach, octm_detach),
DEVMETHOD(device_shutdown, octm_shutdown),
{ 0, 0 }
};
@ -464,7 +463,7 @@ octm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
}
sc->sc_flags = ifp->if_flags;
return (0);
case SIOCSIFCAP:
/*
* Just change the capabilities in software, currently none
@ -484,7 +483,7 @@ octm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
if (error != 0)
return (error);
return (0);
default:
error = ether_ioctl(ifp, cmd, data);
if (error != 0)
@ -513,7 +512,6 @@ octm_rx_intr(void *arg)
return;
}
len = cvmx_mgmt_port_receive(sc->sc_port, MCLBYTES, m->m_data);
if (len > 0) {
m->m_pkthdr.rcvif = sc->sc_ifp;

2
sys/mips/cavium/obio.c
View File

@ -165,7 +165,7 @@ obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_set_rid(rv, *rid);
rman_set_bustag(rv, bt);
rman_set_bushandle(rv, bh);
if (0) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);

2
sys/mips/cavium/obiovar.h
View File

@ -51,7 +51,7 @@ struct obio_softc {
bus_size_t oba_size; /* size of device */
struct rman oba_rman;
struct rman oba_irq_rman;
};
#endif /* _OCTEON_OBIOVAR_H_ */

2
sys/mips/cavium/octe/cavium-ethernet.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -90,7 +89,6 @@ typedef struct {
struct mtx tx_mtx;
} cvm_oct_private_t;
/**
* Free a work queue entry received in a intercept callback.
*

9
sys/mips/cavium/octe/ethernet-common.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -91,7 +90,6 @@ void cvm_oct_common_set_multicast_list(struct ifnet *ifp)
}
}
/**
* Assign a MAC addres from the pool of available MAC addresses
* Can return as either a 64-bit value and/or 6 octets.
@ -116,7 +114,7 @@ int cvm_assign_mac_address(uint64_t *macp, uint8_t *octets)
if (cvm_oct_mac_addr_offset >= cvmx_sysinfo_get()->mac_addr_count)
return ENXIO; /* Out of addresses to assign */
if (macp)
*macp = cvm_oct_mac_addr;
if (octets)
@ -165,7 +163,6 @@ void cvm_oct_common_set_mac_address(struct ifnet *ifp, const void *addr)
}
}
/**
* Change the link MTU. Unimplemented
*
@ -210,7 +207,6 @@ int cvm_oct_common_change_mtu(struct ifnet *ifp, int new_mtu)
return 0;
}
/**
* Enable port.
*/
@ -240,7 +236,6 @@ int cvm_oct_common_open(struct ifnet *ifp)
return 0;
}
/**
* Disable port.
*/
@ -298,7 +293,6 @@ void cvm_oct_common_poll(struct ifnet *ifp)
priv->need_link_update = 1;
}
/**
* Per network device initialization
*
@ -344,4 +338,3 @@ void cvm_oct_common_uninit(struct ifnet *ifp)
{
/* Currently nothing to do */
}

2
sys/mips/cavium/octe/ethernet-common.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -54,4 +53,3 @@ int cvm_oct_sgmii_init(struct ifnet *ifp);
int cvm_oct_spi_init(struct ifnet *ifp);
void cvm_oct_spi_uninit(struct ifnet *ifp);
int cvm_oct_xaui_init(struct ifnet *ifp);

2
sys/mips/cavium/octe/ethernet-defines.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -50,4 +49,3 @@ AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR W
#define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t))
#define TOTAL_NUMBER_OF_PORTS (CVMX_PIP_NUM_INPUT_PORTS+1)

1
sys/mips/cavium/octe/ethernet-headers.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

3
sys/mips/cavium/octe/ethernet-mdio.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -85,7 +84,6 @@ int cvm_oct_mdio_read(struct ifnet *ifp, int phy_id, int location)
return 0;
}
/**
* Perform an MII write. Called by the generic MII routines
*
@ -135,4 +133,3 @@ int cvm_oct_mdio_setup_device(struct ifnet *ifp)
return 0;
}

2
sys/mips/cavium/octe/ethernet-mdio.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -39,4 +38,3 @@ extern struct mtx cvm_oct_mdio_mtx;
int cvm_oct_mdio_read(struct ifnet *ifp, int phy_id, int location);
void cvm_oct_mdio_write(struct ifnet *ifp, int phy_id, int location, int val);
int cvm_oct_mdio_setup_device(struct ifnet *ifp);

2
sys/mips/cavium/octe/ethernet-mem.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -74,7 +73,6 @@ int cvm_oct_mem_fill_fpa(int pool, int size, int elements)
return (elements - freed);
}
/**
* Free the supplied hardware pool of mbufs
*

2
sys/mips/cavium/octe/ethernet-mem.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -32,4 +31,3 @@ AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR W
int cvm_oct_mem_fill_fpa(int pool, int size, int elements);
void cvm_oct_mem_empty_fpa(int pool, int size, int elements);

18
sys/mips/cavium/octe/ethernet-rgmii.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -71,11 +70,9 @@ static void cvm_oct_rgmii_poll(struct ifnet *ifp)
link_info = cvmx_helper_link_get(priv->port);
if (link_info.u64 == priv->link_info) {
/* If the 10Mbps preamble workaround is supported and we're
at 10Mbps we may need to do some special checking */
if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
/* Read the GMXX_RXX_INT_REG[PCTERR] bit and
see if we are getting preamble errors */
int interface = INTERFACE(priv->port);
@ -83,7 +80,6 @@ static void cvm_oct_rgmii_poll(struct ifnet *ifp)
cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
if (gmxx_rxx_int_reg.s.pcterr) {
/* We are getting preamble errors at 10Mbps.
Most likely the PHY is giving us packets
with mis aligned preambles. In order to get
@ -116,7 +112,6 @@ static void cvm_oct_rgmii_poll(struct ifnet *ifp)
every speed change. If errors occur during 10Mbps operation
the above code will change this stuff */
if (USE_10MBPS_PREAMBLE_WORKAROUND) {
cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
cvmx_gmxx_rxx_int_reg_t gmxx_rxx_int_reg;
@ -144,7 +139,6 @@ static void cvm_oct_rgmii_poll(struct ifnet *ifp)
mtx_unlock_spin(&global_register_lock);
}
static int cvm_oct_rgmii_rml_interrupt(void *dev_id)
{
cvmx_npi_rsl_int_blocks_t rsl_int_blocks;
@ -155,18 +149,15 @@ static int cvm_oct_rgmii_rml_interrupt(void *dev_id)
/* Check and see if this interrupt was caused by the GMX0 block */
if (rsl_int_blocks.s.gmx0) {
int interface = 0;
/* Loop through every port of this interface */
for (index = 0; index < cvmx_helper_ports_on_interface(interface); index++) {
/* Read the GMX interrupt status bits */
cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
/* Poll the port if inband status changed */
if (gmx_rx_int_reg.s.phy_dupx || gmx_rx_int_reg.s.phy_link || gmx_rx_int_reg.s.phy_spd) {
struct ifnet *ifp = cvm_oct_device[cvmx_helper_get_ipd_port(interface, index)];
if (ifp)
cvm_oct_rgmii_poll(ifp);
@ -182,18 +173,15 @@ static int cvm_oct_rgmii_rml_interrupt(void *dev_id)
/* Check and see if this interrupt was caused by the GMX1 block */
if (rsl_int_blocks.s.gmx1) {
int interface = 1;
/* Loop through every port of this interface */
for (index = 0; index < cvmx_helper_ports_on_interface(interface); index++) {
/* Read the GMX interrupt status bits */
cvmx_gmxx_rxx_int_reg_t gmx_rx_int_reg;
gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(index, interface));
/* Poll the port if inband status changed */
if (gmx_rx_int_reg.s.phy_dupx || gmx_rx_int_reg.s.phy_link || gmx_rx_int_reg.s.phy_spd) {
struct ifnet *ifp = cvm_oct_device[cvmx_helper_get_ipd_port(interface, index)];
if (ifp)
cvm_oct_rgmii_poll(ifp);
@ -209,7 +197,6 @@ static int cvm_oct_rgmii_rml_interrupt(void *dev_id)
return return_status;
}
int cvm_oct_rgmii_init(struct ifnet *ifp)
{
struct octebus_softc *sc;
@ -257,9 +244,7 @@ int cvm_oct_rgmii_init(struct ifnet *ifp)
a RGMII port */
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
(priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
@ -286,9 +271,7 @@ void cvm_oct_rgmii_uninit(struct ifnet *ifp)
a RGMII port */
if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII) && (priv->port == 0)) ||
(priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
cvmx_gmxx_rxx_int_en_t gmx_rx_int_en;
int interface = INTERFACE(priv->port);
int index = INDEX(priv->port);
@ -307,4 +290,3 @@ void cvm_oct_rgmii_uninit(struct ifnet *ifp)
if (number_rgmii_ports == 0)
panic("%s: need to implement IRQ release.", __func__);
}

9
sys/mips/cavium/octe/ethernet-rx.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -82,7 +81,6 @@ int cvm_oct_do_interrupt(void *dev_id)
return FILTER_HANDLED;
}
/**
* This is called on receive errors, and determines if the packet
* can be dropped early-on in cvm_oct_tasklet_rx().
@ -98,7 +96,6 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
Note these packets still get counted as frame errors. */
} else
if (USE_10MBPS_PREAMBLE_WORKAROUND && ((work->word2.snoip.err_code == 5) || (work->word2.snoip.err_code == 7))) {
/* We received a packet with either an alignment error or a
FCS error. This may be signalling that we are running
10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK} off. If this is the
@ -109,7 +106,6 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
cvmx_gmxx_rxx_frm_ctl_t gmxx_rxx_frm_ctl;
gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
uint8_t *ptr = cvmx_phys_to_ptr(work->packet_ptr.s.addr);
int i = 0;
@ -201,7 +197,6 @@ void cvm_oct_tasklet_rx(void *context, int pending)
CVMX_PREFETCH(cvm_oct_device[work->word1.cn38xx.ipprt], 0);
//CVMX_PREFETCH(m, 0);
rx_count++;
/* Immediately throw away all packets with receive errors */
if ((work->word2.snoip.rcv_error)) {
@ -224,7 +219,6 @@ void cvm_oct_tasklet_rx(void *context, int pending)
*/
m->m_data += (work->packet_ptr.s.back << 7) + (work->packet_ptr.s.addr & 0x7f);
} else {
/* We have to copy the packet. First allocate an
mbuf for it */
MGETHDR(m, M_NOWAIT, MT_DATA);
@ -362,8 +356,6 @@ void cvm_oct_tasklet_rx(void *context, int pending)
}
}
void cvm_oct_rx_initialize(void)
{
int cpu;
@ -385,4 +377,3 @@ void cvm_oct_rx_shutdown(void)
{
panic("%s: not yet implemented.", __func__);
}

2
sys/mips/cavium/octe/ethernet-rx.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -36,4 +35,3 @@ void cvm_oct_tasklet_rx(void *context, int pending);
void cvm_oct_rx_initialize(void);
void cvm_oct_rx_shutdown(void);

1
sys/mips/cavium/octe/ethernet-sgmii.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

8
sys/mips/cavium/octe/ethernet-spi.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -68,7 +67,6 @@ static int cvm_oct_spi_rml_interrupt(void *dev_id)
spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1));
cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64);
if (!need_retrain[1]) {
spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
if (spx_int_reg.s.spf)
printf("SPI1: SRX Spi4 interface down\n");
@ -97,7 +95,6 @@ static int cvm_oct_spi_rml_interrupt(void *dev_id)
stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1));
cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64);
if (!need_retrain[1]) {
stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
if (stx_int_reg.s.syncerr)
printf("SPI1: STX Interface encountered a fatal error\n");
@ -132,7 +129,6 @@ static int cvm_oct_spi_rml_interrupt(void *dev_id)
spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0));
cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64);
if (!need_retrain[0]) {
spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
if (spx_int_reg.s.spf)
printf("SPI0: SRX Spi4 interface down\n");
@ -161,7 +157,6 @@ static int cvm_oct_spi_rml_interrupt(void *dev_id)
stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0));
cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64);
if (!need_retrain[0]) {
stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
if (stx_int_reg.s.syncerr)
printf("SPI0: STX Interface encountered a fatal error\n");
@ -229,9 +224,7 @@ static void cvm_oct_spi_poll(struct ifnet *ifp)
int interface;
for (interface = 0; interface < 2; interface++) {
if ((priv->port == interface*16) && need_retrain[interface]) {
if (cvmx_spi_restart_interface(interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) {
need_retrain[interface] = 0;
cvm_oct_spi_enable_error_reporting(interface);
@ -256,7 +249,6 @@ static void cvm_oct_spi_poll(struct ifnet *ifp)
}
}
int cvm_oct_spi_init(struct ifnet *ifp)
{
struct octebus_softc *sc;

3
sys/mips/cavium/octe/ethernet-tx.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -57,7 +56,6 @@ __FBSDID("$FreeBSD$");
#define GET_MBUF_QOS(m) 0
#endif
/**
* Packet transmit
*
@ -257,7 +255,6 @@ int cvm_oct_xmit(struct mbuf *m, struct ifnet *ifp)
return dropped;
}
/**
* This function frees all mbufs that are currenty queued for TX.
*

2
sys/mips/cavium/octe/ethernet-tx.h
View File

@ -4,7 +4,6 @@
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -32,4 +31,3 @@ AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR W
int cvm_oct_xmit(struct mbuf *m, struct ifnet *ifp);
void cvm_oct_tx_shutdown(struct ifnet *ifp);

4
sys/mips/cavium/octe/ethernet-util.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -44,7 +43,6 @@ static inline char *cvm_oct_get_buffer_ptr(cvmx_buf_ptr_t packet_ptr)
return cvmx_phys_to_ptr(((packet_ptr.s.addr >> 7) - packet_ptr.s.back) << 7);
}
/**
* Given an IPD/PKO port number, return the logical interface it is
* on.
@ -67,7 +65,6 @@ static inline int INTERFACE(int ipd_port)
panic("Illegal ipd_port %d passed to INTERFACE\n", ipd_port);
}
/**
* Given an IPD/PKO port number, return the port's index on a
* logical interface.
@ -83,4 +80,3 @@ static inline int INDEX(int ipd_port)
else
return ipd_port & 3;
}

1
sys/mips/cavium/octe/ethernet-xaui.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

6
sys/mips/cavium/octe/ethernet.c
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
@ -251,7 +250,6 @@ static void cvm_oct_configure_common_hw(device_t bus)
return;
}
#ifdef SMP
{
cvmx_ciu_intx0_t en;
@ -269,7 +267,6 @@ static void cvm_oct_configure_common_hw(device_t bus)
#endif
}
/**
* Free a work queue entry received in a intercept callback.
*
@ -295,7 +292,6 @@ int cvm_oct_free_work(void *work_queue_entry)
return 0;
}
/**
* Module/ driver initialization. Creates the linux network
* devices.
@ -379,7 +375,6 @@ int cvm_oct_init_module(device_t bus)
TASK_INIT(&priv->link_task, 0, cvm_oct_update_link, priv);
switch (priv->imode) {
/* These types don't support ports to IPD/PKO */
case CVMX_HELPER_INTERFACE_MODE_DISABLED:
case CVMX_HELPER_INTERFACE_MODE_PCIE:
@ -463,7 +458,6 @@ int cvm_oct_init_module(device_t bus)
return 0;
}
/**
* Module / driver shutdown
*

1
sys/mips/cavium/octe/mv88e61xxphy.c
View File

@ -617,7 +617,6 @@ static device_method_t mv88e61xxphy_methods[] = {
DEVMETHOD(device_attach, mv88e61xxphy_attach),
DEVMETHOD(device_detach, bus_generic_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};

5
sys/mips/cavium/octe/octe.c
View File

@ -112,7 +112,6 @@ static device_method_t octe_methods[] = {
/* MII interface */
DEVMETHOD(miibus_readreg, octe_miibus_readreg),
DEVMETHOD(miibus_writereg, octe_miibus_writereg),
{ 0, 0 }
};
@ -454,7 +453,7 @@ octe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
}
priv->if_flags = ifp->if_flags;
return (0);
case SIOCSIFCAP:
/*
* Just change the capabilities in software, currently none
@ -483,7 +482,7 @@ octe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
if (error != 0)
return (error);
return (0);
default:
error = ether_ioctl(ifp, cmd, data);
if (error != 0)

1
sys/mips/cavium/octe/octebus.c
View File

@ -66,7 +66,6 @@ static device_method_t octebus_methods[] = {
/* Bus interface. */
DEVMETHOD(bus_add_child, bus_generic_add_child),
{ 0, 0 }
};

1
sys/mips/cavium/octe/wrapper-cvmx-includes.h
View File

@ -4,7 +4,6 @@ SPDX-License-Identifier: BSD-3-Clause
Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

6
sys/mips/cavium/octeon_ds1337.c
View File

@ -38,11 +38,6 @@
*
***********************license end**************************************/
/**
* @file
*
@ -103,7 +98,6 @@ uint32_t cvmx_rtc_ds1337_read(void)
struct clocktime ct;
struct timespec ts;
memset(&reg, 0, sizeof(reg));
memset(&ct, 0, sizeof(ct));

15
sys/mips/cavium/octeon_ebt3000_cf.c
View File

@ -192,7 +192,6 @@ static int cf_send_cmd(uint32_t, uint8_t);
/* Miscelenous */
static void cf_swap_ascii(unsigned char[], char[]);
/* ------------------------------------------------------------------- *
* cf_access() *
* ------------------------------------------------------------------- */
@ -201,7 +200,6 @@ static int cf_access (struct g_provider *pp, int r, int w, int e)
return (0);
}
/* ------------------------------------------------------------------- *
* cf_start() *
* ------------------------------------------------------------------- */
@ -251,13 +249,11 @@ static void cf_start (struct bio *bp)
g_io_deliver(bp, 0);
}
static int cf_ioctl (struct g_provider *pp, u_long cmd, void *data, int fflag, struct thread *td)
{
return (0);
}
static uint8_t cf_inb_8(int port)
{
/*
@ -367,7 +363,6 @@ static int cf_cmd_read (uint32_t nr_sectors, uint32_t start_sector, void *buf)
return (0);
}
/* ------------------------------------------------------------------- *
* cf_cmd_write() *
* ------------------------------------------------------------------- *
@ -381,7 +376,7 @@ static int cf_cmd_write (uint32_t nr_sectors, uint32_t start_sector, void *buf)
uint16_t *ptr_16;
uint8_t *ptr_8;
int error;
lba = start_sector;
ptr_8 = (uint8_t*)buf;
ptr_16 = (uint16_t*)buf;
@ -419,7 +414,6 @@ static int cf_cmd_write (uint32_t nr_sectors, uint32_t start_sector, void *buf)
return (0);
}
/* ------------------------------------------------------------------- *
* cf_cmd_identify() *
* ------------------------------------------------------------------- *
@ -476,7 +470,6 @@ static int cf_cmd_identify(struct cf_priv *cf_priv)
return (0);
}
/* ------------------------------------------------------------------- *
* cf_send_cmd() *
* ------------------------------------------------------------------- *
@ -586,7 +579,6 @@ static void cf_swap_ascii (unsigned char str1[], char str2[])
str2[i] = str1[i ^ 1];
}
/* ------------------------------------------------------------------- *
* cf_probe() *
* ------------------------------------------------------------------- */
@ -620,7 +612,7 @@ static void cf_identify (driver_t *drv, device_t parent)
int count = 0;
cvmx_mio_boot_reg_cfgx_t cfg;
uint64_t phys_base;
if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
return;
@ -672,7 +664,6 @@ static void cf_identify (driver_t *drv, device_t parent)
BUS_ADD_CHILD(parent, 0, "cf", 0);
}
/* ------------------------------------------------------------------- *
* cf_attach_geom() *
* ------------------------------------------------------------------- */
@ -718,7 +709,6 @@ static int cf_attach (device_t dev)
return 0;
}
static device_method_t cf_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, cf_probe),
@ -726,7 +716,6 @@ static device_method_t cf_methods[] = {
DEVMETHOD(device_attach, cf_attach),
DEVMETHOD(device_detach, bus_generic_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};

4
sys/mips/cavium/octeon_gpio.c
View File

@ -322,7 +322,7 @@ octeon_gpio_filter(void *arg)
void **cookie = arg;
struct octeon_gpio_softc *sc = *cookie;
long int irq = (cookie - sc->gpio_intr_cookies);
if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS))
return (FILTER_STRAY);
@ -383,7 +383,7 @@ octeon_gpio_attach(device_t dev)
struct octeon_gpio_softc *sc = device_get_softc(dev);
struct octeon_gpio_pin *pinp;
cvmx_gpio_bit_cfgx_t gpio_cfgx;
int i;
KASSERT((device_get_unit(dev) == 0),

1
sys/mips/cavium/octeon_machdep.c
View File

@ -342,7 +342,6 @@ platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
cvmx_sysinfo_get()->mac_addr_base, ":",
cvmx_sysinfo_get()->mac_addr_count);
octeon_ciu_reset();
/*
* Convert U-Boot 'bootoctlinux' loader command line arguments into

1
sys/mips/cavium/octeon_rnd.c
View File

@ -63,7 +63,6 @@ static device_method_t octeon_rnd_methods[] = {
DEVMETHOD(device_probe, octeon_rnd_probe),
DEVMETHOD(device_attach, octeon_rnd_attach),
DEVMETHOD(device_detach, octeon_rnd_detach),
{ 0, 0 }
};

1
sys/mips/cavium/octeon_rtc.c
View File

@ -58,7 +58,6 @@ static device_method_t octeon_rtc_methods[] = {
/* clock interface */
DEVMETHOD(clock_gettime, octeon_rtc_gettime),
DEVMETHOD(clock_settime, octeon_rtc_settime),
{ 0, 0 }
};

2
sys/mips/cavium/octopci.c
View File

@ -216,7 +216,7 @@ static int
octopci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct octopci_softc *sc;
sc = device_get_softc(dev);
switch (which) {

2
sys/mips/cavium/octopci_bus_space.c
View File

@ -258,7 +258,6 @@ octopci_bs_r_4(void *t, bus_space_handle_t handle,
return (rd32(handle + offset));
}
void
octopci_bs_rm_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, uint8_t *addr, size_t count)
@ -288,7 +287,6 @@ octopci_bs_rm_4(void *t, bus_space_handle_t bsh,
*addr++ = rd32(baddr);
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into

1
sys/mips/cavium/octopcireg.h
View File

@ -90,7 +90,6 @@ typedef union
} s;
} octeon_pci_io_space_address_t;
#define CVMX_OCT_SUBDID_PCI_CFG 1
#define CVMX_OCT_SUBDID_PCI_IO 2
#define CVMX_OCT_SUBDID_PCI_MEM1 3

6
sys/mips/cavium/uart_dev_oct16550.c
View File

@ -55,7 +55,6 @@
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
@ -121,7 +120,7 @@ oct16550_delay (struct uart_bas *bas)
uart_barrier(bas);
uart_setreg(bas, REG_LCR, lcr);
uart_barrier(bas);
if(!bas->rclk)
return 10; /* return an approx delay value */
@ -598,7 +597,6 @@ oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
return (error);
}
static int
oct16550_bus_ipend(struct uart_softc *sc)
{
@ -611,7 +609,6 @@ oct16550_bus_ipend(struct uart_softc *sc)
iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
if (iir != IIR_NOPEND) {
if (iir == IIR_RLS) {
lsr = uart_getreg(bas, REG_LSR);
if (lsr & LSR_OE)
@ -699,7 +696,6 @@ oct16550_bus_probe (struct uart_softc *sc)
sc->sc_txfifosz = 1;
#endif
#if 0
/*
* XXX there are some issues related to hardware flow control and

12
sys/mips/cavium/usb/octusb.c
View File

@ -293,7 +293,6 @@ octusb_host_control_header_tx(struct octusb_td *td)
}
/* do control IN request */
if (td->qh->fixup_buf[0] & UE_DIR_IN) {
struct octusb_softc *sc;
/* get softc */
@ -401,7 +400,6 @@ octusb_host_control_status_tx(struct octusb_td *td)
}
/* do control IN request */
if (!(td->qh->fixup_buf[0] & UE_DIR_IN)) {
struct octusb_softc *sc;
/* get softc */
@ -547,7 +545,6 @@ octusb_non_control_data_rx(struct octusb_td *td)
got_short = 0;
if (td->qh->fixup_complete != 0) {
/* invalidate data */
usb_pc_cpu_invalidate(td->qh->fixup_pc);
@ -769,7 +766,6 @@ octusb_standard_done(struct usb_xfer *xfer)
xfer->td_transfer_cache = xfer->td_transfer_first;
if (xfer->flags_int.control_xfr) {
if (xfer->flags_int.control_hdr)
error = octusb_standard_done_sub(xfer);
@ -779,7 +775,6 @@ octusb_standard_done(struct usb_xfer *xfer)
goto done;
}
while (xfer->aframes != xfer->nframes) {
error = octusb_standard_done_sub(xfer);
xfer->aframes++;
@ -832,7 +827,6 @@ octusb_start_standard_chain(struct usb_xfer *xfer)
/* poll one time */
if (octusb_xfer_do_fifo(xfer)) {
/* put transfer on interrupt queue */
usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
@ -1019,9 +1013,7 @@ octusb_setup_standard_chain(struct usb_xfer *xfer)
/* check if we should prepend a setup message */
if (xfer->flags_int.control_xfr) {
if (xfer->flags_int.control_hdr) {
temp.func = &octusb_host_control_header_tx;
temp.len = xfer->frlengths[0];
temp.pc = xfer->frbuffers + 0;
@ -1060,7 +1052,6 @@ octusb_setup_standard_chain(struct usb_xfer *xfer)
temp.pc = xfer->frbuffers + x;
}
while (x != xfer->nframes) {
/* DATA0 or DATA1 message */
temp.len = xfer->frlengths[x];
@ -1077,13 +1068,11 @@ octusb_setup_standard_chain(struct usb_xfer *xfer)
}
}
if (temp.len == 0) {
/* make sure that we send an USB packet */
temp.short_pkt = 0;
} else {
/* regular data transfer */
temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
@ -1104,7 +1093,6 @@ octusb_setup_standard_chain(struct usb_xfer *xfer)
if (xfer->flags_int.control_xfr &&
!xfer->flags_int.control_act) {
temp.func = &octusb_host_control_status_tx;
temp.len = 0;
temp.pc = NULL;

2
sys/mips/cavium/usb/octusb.h
View File

@ -58,7 +58,6 @@ struct octusb_td {
};
struct octusb_qh {
uint64_t fixup_phys;
struct octusb_softc *sc;
@ -110,7 +109,6 @@ struct octusb_port {
};
struct octusb_softc {
struct usb_bus sc_bus; /* base device */
union octusb_hub_desc sc_hub_desc;

1
sys/mips/cavium/usb/octusb_octeon.c
View File

@ -143,7 +143,6 @@ octusb_octeon_attach(device_t dev)
}
device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus);
err = octusb_init(&sc->sc_dci);
if (!err) {
err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev);

11
sys/mips/include/bus.h
View File

@ -236,7 +236,6 @@ struct bus_space {
bus_size_t, const u_int64_t *, bus_size_t);
};
/*
* Utility macros; INTERNAL USE ONLY.
*/
@ -262,7 +261,6 @@ struct bus_space {
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
/*
* Mapping and unmapping operations.
*/
@ -273,7 +271,6 @@ struct bus_space {
#define bus_space_subregion(t, h, o, s, hp) \
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
/*
* Allocation and deallocation operations.
*/
@ -326,7 +323,6 @@ struct bus_space {
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
/*
* Bus read region operations.
*/
@ -348,7 +344,6 @@ struct bus_space {
#define bus_space_read_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
/*
* Bus write (single) operations.
*/
@ -362,7 +357,6 @@ struct bus_space {
#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
/*
* Bus write multiple operations.
*/
@ -384,7 +378,6 @@ struct bus_space {
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
/*
* Bus write region operations.
*/
@ -406,7 +399,6 @@ struct bus_space {
#define bus_space_write_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
/*
* Set multiple operations.
*/
@ -419,7 +411,6 @@ struct bus_space {
#define bus_space_set_multi_8(t, h, o, v, c) \
__bs_set(sm,8,(t),(h),(o),(v),(c))
/*
* Set region operations.
*/
@ -432,7 +423,6 @@ struct bus_space {
#define bus_space_set_region_8(t, h, o, v, c) \
__bs_set(sr,8,(t),(h),(o),(v),(c))
/*
* Copy operations.
*/
@ -715,7 +705,6 @@ void __bs_c(f,_bs_c_8) (void *t, bus_space_handle_t bsh1, \
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFUL
#endif
#define BUS_SPACE_UNRESTRICTED (~0)
/*

2
sys/mips/include/cpufunc.h
View File

@ -379,7 +379,7 @@ get_intr_mask(void)
#if !defined(__mips_o32)
#define readq(a) (*(volatile uint64_t *)(a))
#endif
#define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
#define writew(va, d) (*(volatile uint16_t *) (va) = (d))
#define writel(va, d) (*(volatile uint32_t *) (va) = (d))

4
sys/mips/include/cpuregs.h
View File

@ -421,7 +421,6 @@
#define _(n) n
#endif
#define MIPS_COP_0_TLB_INDEX _(0)
#define MIPS_COP_0_TLB_RANDOM _(1)
/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
@ -498,7 +497,7 @@
#define MIPS_CONFIG0_MT_SHIFT 7
#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
#define MIPS_CONFIG0_VI 0x00000008 /* inst cache is virtual */
/*
* Config1 Register Fields
* (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9-1)
@ -620,7 +619,6 @@
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
#define MIPS_FPC_MBZ_BITS 0xfe7c0000
/*
* Constants to determine if have a floating point instruction.
*/

1
sys/mips/include/db_machdep.h
View File

@ -68,7 +68,6 @@ db_addr_t next_instr_address(db_addr_t, boolean_t);
} \
} while (0);
/*
* Test of instructions to see class.
*/

1
sys/mips/include/mips_opcode.h
View File

@ -138,7 +138,6 @@ typedef union {
#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07))
/*
* Values for the 'op' field.
*/

1
sys/mips/include/regnum.h
View File

@ -126,7 +126,6 @@
#define TA3 15
#endif
/*
* Index of FP registers in 'struct frame', counting from the beginning
* of the frame (i.e., including the general registers).

1
sys/mips/ingenic/jz4780_clk_gen.c
View File

@ -290,7 +290,6 @@ jz4780_clk_gen_set_gate(struct clknode *clk, bool enable)
return (0);
}
int jz4780_clk_gen_register(struct clkdom *clkdom,
const struct jz4780_clk_descr *descr, struct mtx *dev_mtx,
struct resource *mem_res)

1
sys/mips/ingenic/jz4780_clock.c
View File

@ -451,7 +451,6 @@ jz4780_clock_register(struct jz4780_clock_softc *sc)
ret = clknode_gate_register(sc->clkdom, &gatedef);
if (ret != 0)
return (ret);
}
return (0);

1
sys/mips/ingenic/jz4780_machdep.c
View File

@ -141,7 +141,6 @@ mips_init(void)
#ifdef FDT
if (fdt_get_mem_regions(mr, &mr_cnt, &val) == 0) {
physmem = realmem = btoc(val);
KASSERT((phys_avail[0] >= mr[0].mr_start) && \

2
sys/mips/ingenic/jz4780_pdma.c
View File

@ -451,7 +451,7 @@ pdma_channel_request(device_t dev, struct xdma_channel *xchan, struct xdma_reque
chan->flags = CHAN_DESCR_RELINK;
chan->cur_desc = 0;
chan->req = req;
for (i = 0; i < req->block_num; i++) {
desc = &chan->desc_ring[i];

1
sys/mips/ingenic/jz4780_pinctrl.c
View File

@ -240,7 +240,6 @@ jz4780_pinctrl_configure_pins(device_t dev, phandle_t cfgxref)
return (result);
}
static device_method_t jz4780_pinctrl_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, jz4780_pinctrl_probe),

1
sys/mips/ingenic/jz4780_pinctrl.h
View File

@ -29,5 +29,4 @@
#ifndef _MIPS_INGENIC_JZ4780_PINCTRL_H
#define _MIPS_INGENIC_JZ4780_PINCTRL_H
#endif /* _MIPS_INGENIC_JZ4780_PINCTRL_H */

1
sys/mips/ingenic/jz4780_timer.c
View File

@ -336,4 +336,3 @@ platform_initclocks(void)
{
}

3
sys/mips/malta/gt.c
View File

@ -72,7 +72,6 @@ gt_attach(device_t dev)
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
@ -82,7 +81,7 @@ gt_alloc_resource(device_t dev, device_t child, int type, int *rid,
{
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
type, rid, start, end, count, flags));
}
static int

3
sys/mips/malta/gt_pci.c
View File

@ -317,7 +317,6 @@ gt_pci_attach(device_t dev)
sc->sc_ioh_icu2 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU2);
#endif
/* All interrupts default to "masked off". */
sc->sc_imask = 0xffff;
@ -680,7 +679,7 @@ gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
{
bus_space_handle_t p;
int error;
if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
error = bus_space_map(rman_get_bustag(r),
rman_get_bushandle(r), rman_get_size(r), 0, &p);

2
sys/mips/malta/gtreg.h
View File

@ -34,8 +34,6 @@
* $FreeBSD$
*/
#define GT_REGVAL(x) *((volatile u_int32_t *) \
(MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))

2
sys/mips/malta/malta_machdep.c
View File

@ -134,7 +134,7 @@ static void
malta_lcd_print(char *str)
{
int i;
if (str == NULL)
return;

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