Fix typos, document UMASK values.
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2020-12-20 02:59:44 +00:00
svn path=/head/; revision=184916
@ -226,48 +226,48 @@ The default is to measure both snoops.
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Core2 programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li BACLEARS
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.Pq Event E6H
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.Pq Event E6H , Umask 00H
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The number of times the front end is resteered.
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.It Li BOGUS_BR
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.Pq Event E4H
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.Pq Event E4H , Umask 00H
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The number of byte sequences mistakenly detected as taken branch
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instructions.
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.It Li BR_BAC_MISSP_EXEC
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.Pq Event 8AH
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.Pq Event 8AH , Umask 00H
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The number of branch instructions that were mispredicted when
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decoded.
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.It Li BR_CALL_MISSP_EXEC
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.Pq Event 93H
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.Pq Event 93H , Umask 00H
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The number of mispredicted
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.Li CALL
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instructions that were executed.
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.It Li BR_CALL_EXEC
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.Pq Event 92H
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.Pq Event 92H , Umask 00H
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The number of
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.Li CALL
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instructions executed.
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.It Li BR_CND_EXEC
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.Pq Event 8BH
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.Pq Event 8BH , Umask 00H
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The number of conditional branches executed, but not necessarily retired.
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.It Li BR_CND_MISSP_EXEC
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.Pq Event 8CH
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.Pq Event 8CH , Umask 00H
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The number of mispredicted conditional branches executed.
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.It Li BR_IND_CALL_EXEC
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.Pq Event 94H
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.Pq Event 94H , Umask 00H
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The number of indirect
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.Li CALL
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instructions executed.
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.It Li BR_IND_EXEC
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.Pq Event 8DH
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.Pq Event 8DH , Umask 00H
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The number of indirect branch instructions executed.
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.It Li BR_IND_MISSP_EXEC
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.Pq Event 8EH
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.Pq Event 8EH , Umask 00H
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The number of mispredicted indirect branch instructions executed.
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.It Li BR_INST_DECODED
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.Pq Event E0H
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.Pq Event E0H , Umask 00H
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The number of branch instructions decoded.
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.It Li BR_INST_EXEC
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.Pq Event 88H
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.Pq Event 88H , Umask 00H
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The number of branches executed, but not necessarily retired.
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.It Li BR_INST_RETIRED.ANY
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.Pq Event C4H , Umask 00H
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@ -298,28 +298,28 @@ predicted.
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.Pq Event C4H , Umask 0CH
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The number of taken branch instructions retired.
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.It Li BR_MISSP_EXEC
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.Pq Event 89H
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.Pq Event 89H , Umask 00H
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The number of mispredicted branch instructions that were executed.
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.It Li BR_RET_MISSP_EXEC
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.Pq Event 90H
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.Pq Event 90H , Umask 00H
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The number of mispredicted
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.Li RET
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instructions executed.
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.It Li BR_RET_BAC_MISSP_EXEC
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.Pq Event 91H
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.Pq Event 91H , Umask 00H
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The number of
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.Li RET
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instructions executed that were mispredicted at decode time.
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.It Li BR_RET_EXEC
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.Pq Event 8FH
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.Pq Event 8FH , Umask 00H
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The number of
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.Li RET
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instructions executed.
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.It Li BR_TKN_BUBBLE_1
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.Pq Event 97H
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.Pq Event 97H , Umask 00H
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The number of branch predicted taken with bubble 1.
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.It Li BR_TKN_BUBBLE_2
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.Pq Event 98H
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.Pq Event 98H , Umask 00H
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The number of branch predicted taken with bubble 2.
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.It Li BUSQ_EMPTY Op ,core= Ns Ar core
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.Pq Event 7DH
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@ -463,7 +463,7 @@ This is an architectural performance event.
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The number of bus cycles during which the core remains unhalted and
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the other core is halted.
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.It Li CYCLES_DIV_BUSY
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.Pq Event 14H
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.Pq Event 14H , Umask 00H
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The number of cycles the divider is busy.
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This event is only available on PMC0.
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.It Li CYCLES_INT_MASKED
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@ -474,7 +474,7 @@ The number of cycles during which interrupts are disabled.
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The number of cycles during which there were pending interrupts while
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interrupts were disabled.
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.It Li CYCLES_L1I_MEM_STALLED
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.Pq Event 86H
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.Pq Event 86H , Umask 00H
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The number of cycles for which an instruction fetch stalls.
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.It Li DELAYED_BYPASS.FP
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.Pq Event 19H , Umask 00H
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@ -488,7 +488,7 @@ The number of delayed bypass penalty cycles that a load operation incurred.
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The number of times SIMD operations use data immediately after data,
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was generated by a non-SIMD execution unit.
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.It Li DIV
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.Pq Event 13H
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.Pq Event 13H , Umask 00H
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The number of divide operations executed.
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This event is only available on PMC1.
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.It Li DTLB_MISSES.ANY
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@ -505,7 +505,7 @@ The number of Data TLB misses due to load operations.
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.Pq Event 08H , Umask 08H
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The number of Data TLB misses due to store operations.
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.It Li EIST_TRANS
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.Pq Event 3AH
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.Pq Event 3AH , Umask 00H
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The number of Enhanced Intel SpeedStep Technology transitions.
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.It Li ESP.ADDITIONS
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.Pq Event ABH , Umask 02H
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@ -529,11 +529,11 @@ instruction.
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.Pq Event 77H
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The number of snoop responses to bus transactions.
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.It Li FP_ASSIST
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.Pq Event 11H
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.Pq Event 11H , Umask 00H
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The number of floating point operations executed that needed
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a microcode assist.
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.It Li FP_COMP_OPS_EXE
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.Pq Event 10H
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.Pq Event 10H , Umask 00H
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The number of floating point computational micro-ops executed.
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The event is available only on PMC0.
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.It Li FP_MMX_TRANS_TO_FP
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@ -545,19 +545,19 @@ instructions.
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The number of transitions from floating point instructions to MMX
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instructions.
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.It Li HW_INT_RCV
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.Pq Event C8H
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.Pq Event C8H , Umask 00H
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The number of hardware interrupts recieved.
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.It Li IDLE_DURING_DIV
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.Pq Event 18H
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.Pq Event 18H , Umask 00H
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The number of cycles the divider is busy and no other execution unit
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or load operation was in progress.
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This event is available only on PMC0.
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.It Li ILD_STALL
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.Pq Event 87H
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.Pq Event 87H , Umask 00H
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The number of cycles the instruction length decoder stalled due to a
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length changing prefix.
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.It Li INST_QUEUE.FULL
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.Pq Event 83H
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.Pq Event 83H , Umask 02H
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The number of cycles during which the instruction queue is full.
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.It Li INST_RETIRED.ANY_P
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.Pq Event C0H , Umask 00H
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@ -568,14 +568,15 @@ This is an architectural performance event.
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.Pq Event C0H , Umask 01H
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The number of instructions retired that contained a load operation.
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.It Li INST_RETIRED.OTHER
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.Pq Event C0H
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.Pq Event C0H , Umask 04H
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The number of instructions retired that did not contain a load or a
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store operation.
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.It Li INST_RETIRED.STORES
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.Pq Event C0H
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.Pq Event C0H , Umask 02H
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The number of instructions retired that contained a store operation.
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.It Li INST_RETIRED.VM_H
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.Pq Event C0H , Tn Core2Extreme
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.Pq Event C0H , Umask 08H
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.Pq Tn Core2Extreme
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The number of instructions retired while in VMX root operation.
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.It Li ITLB.FLUSH
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.Pq Event 82H , Umask 40H
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@ -592,7 +593,7 @@ miss the ITLB.
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.Pq Event 82H , Umask 02H
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The number of instruction fetches from small pages that miss the ITLB.
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.It Li ITLB_MISS_RETIRED
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.Pq Event C9H
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.Pq Event C9H , Umask 00H
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The number of retired instructions that missed the ITLB when they were
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fetched.
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.It Li L1D_ALL_REF
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@ -606,7 +607,7 @@ The number of data reads and writes to cacheable memory.
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.Pq Event 42H
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The number of locked reads from cacheable memory.
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.It Li L1D_CACHE_LOCK_DURATION
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.Pq Event 42H
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.Pq Event 42H , Umask 10H
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The number of cycles during which any cache line is locked by any
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locking instruction.
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.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state
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@ -618,20 +619,20 @@ reads.
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The number of data writes to cacheable memory excluding locked
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writes.
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.It Li L1D_M_EVICT
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.Pq Event 47H
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.Pq Event 47H , Umask 00H
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The number of modified cache lines evicted from L1 data cache.
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.It Li L1D_M_REPL
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.Pq Event 46H
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.Pq Event 46H , Umask 00H
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The number of modified lines allocated in L1 data cache.
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.It Li L1D_PEND_MISS
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.Pq Event 48H
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.Pq Event 48H , Umask 00H
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The total number of outstanding L1 data cache misses at any clock.
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.It Li L1D_PREFETCH.
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.Pq Event 4EH
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.It Li L1D_PREFETCH.REQUESTS
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.Pq Event 4EH , Umask 10H
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The number of times L1 data cache requested to prefetch a data cache
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line.
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.It Li L1D_REPL
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.Pq Event 45H
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.Pq Event 45H , Umask 0FH
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The number of lines brought into L1 data cache.
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.It Li L1D_SPLIT.LOADS
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.Pq Event 49H , Umask 01H
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@ -640,10 +641,10 @@ The number of load operations that span two cache lines.
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.Pq Event 49H , Umask 02H
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The number of store operations that span two cache lines.
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.It Li L1I_MISSES
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.Pq Event 81H
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.Pq Event 81H , Umask 00H
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The number of instruction fetch unit misses.
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.It Li L1I_READS
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.Pq Event 80H
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.Pq Event 80H , Umask 00H
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The number of instruction fetches.
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.It Li L2_ADS Op ,core= Ns core
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.Pq Event 21H
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@ -750,7 +751,7 @@ whose data value is not known.
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.Pq Event 03H , Umask 10H
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The numer of load operations that were blocked until retirement.
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.It Li LOAD_HIT_PRE
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.Pq Event 4CH
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.Pq Event 4CH , Umask 00H
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The number of load operations that conflicted with an prefetch to the
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same cache line.
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.It Li MACHINE_NUKES.SMC
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@ -793,7 +794,7 @@ bus request.
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.Pq Event CBH , Umask 04H
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The number of load operations that missed L2 cache.
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.It Li MUL
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.Pq Event 12H
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.Pq Event 12H , Umask 00H
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The number of multiply operations executed.
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This event is only available on PMC1.
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.It Li PAGE_WALKS.COUNT
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@ -804,11 +805,11 @@ The number of page walks executed due to an ITLB or DTLB miss.
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The number of cycles spent in a page walk caused by an ITLB or DTLB
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miss.
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.It Li PREF_RQSTS_DN
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.Pq Event F8H
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.Pq Event F8H , Umask 00H
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The number of downward prefetches issued from the Data Prefetch Logic
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unit to L2 cache.
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.It Li PREF_RQSTS_UP
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.Pq Event F0H
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.Pq Event F0H , Umask 00H
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The number of upward prefetches issued from the Data Prefetch Logic
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unit to L2 cache.
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.It Li RAT_STALLS.ANY
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@ -882,14 +883,14 @@ The number of cycles micro-ops were dispatched for execution on port
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The number of cycles micro-ops were dispatched for execution on port
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4.
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.It Li RS_UOPS_DISPATCHED.PORT5
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.Pq Event A1H , Umask 20
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.Pq Event A1H , Umask 20H
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The number of cycles micro-ops were dispatched for execution on port
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5.
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.It Li SB_DRAIN_CYCLES
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.Pq Event 04H , Umask 01H
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The number of cycles while the store buffer is draining.
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.It Li SEGMENT_REG_LOADS
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.Pq Event 06H
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.Pq Event 06H , Umask 00H
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The number of segment register loads.
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.It Li SEG_REG_RENAMES.ANY
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.Pq Event D5H , Umask 0FH
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@ -939,7 +940,7 @@ The number of stalls due to lack of renaming resources for the
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.Li %gs
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register.
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.It Li SIMD_ASSIST
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.Pq Event CDH
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.Pq Event CDH , Umask 00H
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The number SIMD assists invoked.
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.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
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.Pq Event CAH , Umask 04H
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@ -958,7 +959,7 @@ retired.
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Then number of computational SSE2 scalar single precision instructions
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retired.
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.It Li SIMD_INSTR_RETIRED
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.Pq Event CEH
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.Pq Event CEH , Umask 00H
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The number of retired SIMD instructions that use MMX registers.
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.It Li SIMD_INST_RETIRED.ANY
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.Pq Event C7H , Umask 1FH
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@ -979,13 +980,13 @@ The number of SSE scalar single precision instructions retired.
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.Pq Event C7H , Umask 10H
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The number of SSE2 vector instructions retired.
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.It Li SIMD_SAT_INSTR_RETIRED
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.Pq Event CFH
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.Pq Event CFH , Umask 00H
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The number of saturated arithmetic SIMD instructions retired.
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.It Li SIMD_SAT_UOP_EXEC
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.Pq Event B1H
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.Pq Event B1H , Umask 00H
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The number of SIMD saturated arithmetic micro-ops executed.
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.It Li SIMD_UOPS_EXEC
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.Pq Event B0H
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.Pq Event B0H , Umask 00H
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The number of SIMD micro-ops executed.
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.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC
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.Pq Event B3H , Umask 20H
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@ -1053,7 +1054,7 @@ globally observed.
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The number of cycles while a store was blocked due to a conflict with
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an internal or external snoop.
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.It Li THERMAL_TRIP
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.Pq Event 3BH
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.Pq Event 3BH , Umask C0H
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The number of thermal trips.
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.It Li UOPS_RETIRED.LD_IND_BR
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.Pq Event C2H , Umask 01H
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