arm64: rockchip: clk: Set the write mask when setting the clock mux

RockChip clocks have a write mask in the upper 16bits of the mux register
which wasn't set in the set_mux function.
Also the wrong parent was tested instead of the real current one, when
switch parent, test with the current one before.

Pointy Hat:    manu
MFC after:	1 week
This commit is contained in:
Emmanuel Vadot 2019-02-25 17:40:00 +00:00
parent d3248c4170
commit f4f53f2b4d
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=344527

View File

@ -128,7 +128,7 @@ rk_clk_composite_set_mux(struct clknode *clk, int index)
READ4(clk, sc->muxdiv_offset, &val);
val &= ~sc->mux_mask;
val |= index << sc->mux_shift;
WRITE4(clk, sc->muxdiv_offset, val);
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_COMPOSITE_MASK);
DEVICE_UNLOCK(clk);
return (0);
@ -222,6 +222,7 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
return (0);
}
p_idx = clknode_get_parent_idx(clk);
if (p_idx != best_parent)
clknode_set_parent_by_idx(clk, best_parent);