Drastically clean up the legacy host-pci bridge table. We don't need
all the ancient Intel/VIA/SIS/etc chipsets on amd64 systems. Even the newer intel stuff won't need this since we use acpi by default and we don't have all their magic programming information. Just use a generic "Host to PCI bridge" name if we ever hit this code.
This commit is contained in:
Peter Wemm
parent
10884719f8
commit
f502c2725e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=126927
@ -33,7 +33,6 @@ __FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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@ -42,9 +41,6 @@ __FBSDID("$FreeBSD$");
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#include <isa/isavar.h>
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#include <machine/legacyvar.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/segments.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include "pcib_if.h"
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@ -88,210 +84,10 @@ legacy_pcib_is_host_bridge(int bus, int slot, int func,
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u_int8_t *busnum)
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{
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const char *s = NULL;
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static u_int8_t pxb[4]; /* hack for 450nx */
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*busnum = 0;
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switch (id) {
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case 0x12258086:
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s = "Intel 824?? host to PCI bridge";
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/* XXX This is a guess */
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/* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
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*busnum = bus;
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break;
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case 0x71208086:
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s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
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break;
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case 0x71228086:
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s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
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break;
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case 0x71248086:
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s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
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break;
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case 0x11308086:
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s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
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break;
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case 0x71808086:
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s = "Intel 82443LX (440 LX) host to PCI bridge";
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break;
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case 0x71908086:
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s = "Intel 82443BX (440 BX) host to PCI bridge";
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break;
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case 0x71928086:
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s = "Intel 82443BX host to PCI bridge (AGP disabled)";
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break;
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case 0x71948086:
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s = "Intel 82443MX host to PCI bridge";
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break;
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case 0x71a08086:
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s = "Intel 82443GX host to PCI bridge";
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break;
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case 0x71a18086:
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s = "Intel 82443GX host to AGP bridge";
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break;
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case 0x71a28086:
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s = "Intel 82443GX host to PCI bridge (AGP disabled)";
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break;
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case 0x84c48086:
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s = "Intel 82454KX/GX (Orion) host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
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break;
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case 0x84ca8086:
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/*
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* For the 450nx chipset, there is a whole bundle of
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* things pretending to be host bridges. The MIOC will
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* be seen first and isn't really a pci bridge (the
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* actual busses are attached to the PXB's). We need to
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* read the registers of the MIOC to figure out the
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* bus numbers for the PXB channels.
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*
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* Since the MIOC doesn't have a pci bus attached, we
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* pretend it wasn't there.
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*/
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pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
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0xd0, 1); /* BUSNO[0] */
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pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
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0xd1, 1) + 1; /* SUBA[0]+1 */
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pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
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0xd3, 1); /* BUSNO[1] */
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pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
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0xd4, 1) + 1; /* SUBA[1]+1 */
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return NULL;
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case 0x84cb8086:
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switch (slot) {
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case 0x12:
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s = "Intel 82454NX PXB#0, Bus#A";
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*busnum = pxb[0];
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break;
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case 0x13:
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s = "Intel 82454NX PXB#0, Bus#B";
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*busnum = pxb[1];
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break;
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case 0x14:
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s = "Intel 82454NX PXB#1, Bus#A";
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*busnum = pxb[2];
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break;
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case 0x15:
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s = "Intel 82454NX PXB#1, Bus#B";
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*busnum = pxb[3];
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break;
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}
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break;
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/* AMD -- vendor 0x1022 */
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case 0x30001022:
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s = "AMD Elan SC520 host to PCI bridge";
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#ifdef CPU_ELAN
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init_AMD_Elan_sc520();
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#else
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printf(
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"*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
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#endif
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break;
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case 0x70061022:
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s = "AMD-751 host to PCI bridge";
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break;
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case 0x700e1022:
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s = "AMD-761 host to PCI bridge";
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break;
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/* SiS -- vendor 0x1039 */
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case 0x04961039:
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s = "SiS 85c496";
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break;
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case 0x04061039:
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s = "SiS 85c501";
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break;
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case 0x06011039:
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s = "SiS 85c601";
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break;
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case 0x55911039:
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s = "SiS 5591 host to PCI bridge";
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break;
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case 0x00011039:
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s = "SiS 5591 host to AGP bridge";
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break;
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/* VLSI -- vendor 0x1004 */
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case 0x00051004:
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s = "VLSI 82C592 Host to PCI bridge";
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break;
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/* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
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/* totally. Please let me know if anything wrong. -F */
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/* XXX need info on the MVP3 -- any takers? */
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case 0x05981106:
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s = "VIA 82C598MVP (Apollo MVP3) host bridge";
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break;
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/* AcerLabs -- vendor 0x10b9 */
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/* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
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/* id is '10b9" but the register always shows "10b9". -Foxfair */
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case 0x154110b9:
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s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
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break;
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/* OPTi -- vendor 0x1045 */
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case 0xc7011045:
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s = "OPTi 82C700 host to PCI bridge";
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break;
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case 0xc8221045:
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s = "OPTi 82C822 host to PCI Bridge";
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break;
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/* ServerWorks -- vendor 0x1166 */
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case 0x00051166:
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s = "ServerWorks NB6536 2.0HE host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00061166:
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/* FALLTHROUGH */
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case 0x00081166:
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/* FALLTHROUGH */
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case 0x02011166:
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/* FALLTHROUGH */
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case 0x010f1014: /* IBM re-badged ServerWorks chipset */
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s = "ServerWorks host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00091166:
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s = "ServerWorks NB6635 3.0LE host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00101166:
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s = "ServerWorks CIOB30 host to PCI bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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case 0x00111166:
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/* FALLTHROUGH */
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case 0x03021014: /* IBM re-badged ServerWorks chipset */
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s = "ServerWorks CMIC-HE host to PCI-X bridge";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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/* XXX unknown chipset, but working */
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case 0x00171166:
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/* FALLTHROUGH */
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case 0x01011166:
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s = "ServerWorks host to PCI bridge(unknown chipset)";
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*busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
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break;
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/* Integrated Micro Solutions -- vendor 0x10e0 */
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case 0x884910e0:
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s = "Integrated Micro Solutions VL Bridge";
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break;
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default:
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if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
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s = "Host to PCI bridge";
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break;
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}
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if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
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s = "Host to PCI bridge";
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return s;
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}
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@ -432,9 +228,10 @@ legacy_pcib_probe(device_t dev)
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int
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legacy_pcib_attach(device_t dev)
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{
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int bus;
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device_add_child(dev, "pci", pcib_get_bus(dev));
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bus = pcib_get_bus(dev);
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device_add_child(dev, "pci", bus);
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return bus_generic_attach(dev);
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}
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