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Always initialize the UPA target module id in the interrupt mapping

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register to the one of the processor doing the interrupt setup. This
is required since this field is preinitialized to 0, but there exist
machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2
processors).

Add some more macros for handle the interrupt mapping registers, and
rename some existing ones for consistency.

Approved by:	re
This commit is contained in:
Thomas Moestl 2002-12-01 23:30:26 +00:00
parent 0aa267f6a7
commit f57d04ab1d
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=107477
3 changed files with 34 additions and 33 deletions
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35
sys/sparc64/include/bus_common.h
View File

@ -48,23 +48,24 @@
#ifndef _MACHINE_BUS_COMMON_H_ #ifndef _MACHINE_BUS_COMMON_H_
#define _MACHINE_BUS_COMMON_H_ #define _MACHINE_BUS_COMMON_H_
#define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */ #define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */
#define INTMAP_TID 0x07c000000LL /* UPA target ID mask */ #define INTMAP_TID_MASK 0x07c000000LL /* UPA target ID */
#define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */ #define INTMAP_TID_SHIFT 26
#define INTMAP_INO 0x00000003fLL /* Interrupt number */ #define INTMAP_IGN_MASK 0x0000007c0LL /* Interrupt group no. */
#define INTMAP_INR (INTMAP_IGN | INTMAP_INO) #define INTMAP_IGN_SHIFT 6
#define INTMAP_SBUSSLOT 0x000000018LL /* SBUS slot # */ #define INTMAP_INO_MASK 0x00000003fLL /* Interrupt number */
#define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */ #define INTMAP_INR_MASK (INTMAP_IGN_MASK | INTMAP_INO_MASK)
#define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */ #define INTMAP_SBUSSLOT_MASK 0x000000018LL /* SBUS slot # */
#define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */ #define INTMAP_PCIBUS_MASK 0x000000010LL /* PCI bus number (A or B) */
#define INTMAP_OBIO 0x000000020LL /* Onboard device */ #define INTMAP_PCISLOT_MASK 0x00000000cLL /* PCI slot # */
#define INTMAP_LSHIFT 11 /* Encode level in vector */ #define INTMAP_PCIINT_MASK 0x000000003LL /* PCI interrupt #A,#B,#C,#D */
#define INTLEVENCODE(x) (((x) & 0x0f) << INTMAP_LSHIFT) #define INTMAP_OBIO_MASK 0x000000020LL /* Onboard device */
#define INTLEV(x) (((x) >> INTMAP_LSHIFT) & 0x0f) #define INTVEC(x) ((x) & INTMAP_INR_MASK)
#define INTVEC(x) ((x) & INTMAP_INR) #define INTSLOT(x) (((x) >> 3) & 0x7)
#define INTSLOT(x) (((x) >> 3) & 0x7) #define INTPRI(x) ((x) & 0x7)
#define INTPRI(x) ((x) & 0x7) #define INTINO(x) ((x) & INTMAP_INO_MASK)
#define INTINO(x) ((x) & INTMAP_INO) #define INTMAP_ENABLE(mr, mid) \
(((mr) & ~INTMAP_TID_MASK) | ((mid) << INTMAP_TID_SHIFT) | INTMAP_V)
/* counter-timer support. */ /* counter-timer support. */
void sparc64_counter_init(bus_space_tag_t tag, bus_space_handle_t handle, void sparc64_counter_init(bus_space_tag_t tag, bus_space_handle_t handle,

14
sys/sparc64/pci/psycho.c
View File

@ -43,6 +43,7 @@
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/kernel.h> #include <sys/kernel.h>
#include <sys/malloc.h> #include <sys/malloc.h>
#include <sys/pcpu.h>
#include <ofw/openfirm.h> #include <ofw/openfirm.h>
#include <ofw/ofw_pci.h> #include <ofw/ofw_pci.h>
@ -576,7 +577,7 @@ psycho_attach(device_t dev)
PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V);
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
PCICTL_WRITE8(sc, clr + i * 8, 0); PCICTL_WRITE8(sc, clr + i * 8, 0);
PSYCHO_WRITE8(sc, map, mr | INTMAP_V); PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
} }
for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0;
map < PSR_FFB0_INT_MAP; map += 8, clr += 8, n++) { map < PSR_FFB0_INT_MAP; map += 8, clr += 8, n++) {
@ -602,7 +603,7 @@ psycho_attach(device_t dev)
psycho_intr_stray, sclr); psycho_intr_stray, sclr);
} }
#endif #endif
PSYCHO_WRITE8(sc, map, mr | INTMAP_V); PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
} }
#endif #endif
@ -657,7 +658,7 @@ psycho_set_intr(struct psycho_softc *sc, int index,
panic("psycho_set_intr: failed to get interrupt"); panic("psycho_set_intr: failed to get interrupt");
bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags,
handler, sc, &sc->sc_ihand[index]); handler, sc, &sc->sc_ihand[index]);
PSYCHO_WRITE8(sc, map, mr | INTMAP_V); PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid)));
} }
static int static int
@ -1126,11 +1127,10 @@ psycho_setup_intr(device_t dev, device_t child,
*/ */
PSYCHO_WRITE8(sc, intrclrptr, 0); PSYCHO_WRITE8(sc, intrclrptr, 0);
/* /*
* Enable the interrupt now we have the handler installed. * Enable the interrupt and program the target module now we have the
* Read the current value as we can't change it besides the * handler installed.
* valid bit so so make sure only this bit is changed.
*/ */
PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid)));
return (error); return (error);
} }

18
sys/sparc64/sbus/sbus.c
View File

@ -111,6 +111,7 @@
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/kernel.h> #include <sys/kernel.h>
#include <sys/malloc.h> #include <sys/malloc.h>
#include <sys/pcpu.h>
#include <sys/reboot.h> #include <sys/reboot.h>
#include <ofw/openfirm.h> #include <ofw/openfirm.h>
@ -318,7 +319,7 @@ sbus_probe(device_t dev)
if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1) if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1)
panic("sbus_probe: cannot get IGN"); panic("sbus_probe: cannot get IGN");
sc->sc_ign = intr & INTMAP_IGN; /* Find interrupt group no */ sc->sc_ign = intr & INTMAP_IGN_MASK; /* Find interrupt group no */
sc->sc_cbustag = sbus_alloc_bustag(sc); sc->sc_cbustag = sbus_alloc_bustag(sc);
/* /*
@ -429,7 +430,7 @@ sbus_probe(device_t dev)
panic("sbus_probe: failed to get temperature interrupt"); panic("sbus_probe: failed to get temperature interrupt");
bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST, bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST,
sbus_overtemp, sc, &sc->sc_ot_ihand); sbus_overtemp, sc, &sc->sc_ot_ihand);
SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, mr | INTMAP_V); SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
rid = 0; rid = 0;
mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP); mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP);
vec = INTVEC(mr); vec = INTVEC(mr);
@ -438,7 +439,7 @@ sbus_probe(device_t dev)
panic("sbus_probe: failed to get power fail interrupt"); panic("sbus_probe: failed to get power fail interrupt");
bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST, bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST,
sbus_pwrfail, sc, &sc->sc_pf_ihand); sbus_pwrfail, sc, &sc->sc_pf_ihand);
SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, mr | INTMAP_V); SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid)));
/* Initialize the counter-timer. */ /* Initialize the counter-timer. */
sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0); sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0);
@ -519,7 +520,7 @@ sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name)
* Sbus card devices need the slot number encoded into * Sbus card devices need the slot number encoded into
* the vector as this is generally not done. * the vector as this is generally not done.
*/ */
if ((iv & INTMAP_OBIO) == 0) if ((iv & INTMAP_OBIO_MASK) == 0)
iv |= slot << 3; iv |= slot << 3;
/* Set the ign as appropriate. */ /* Set the ign as appropriate. */
iv |= sc->sc_ign; iv |= sc->sc_ign;
@ -660,7 +661,7 @@ sbus_setup_intr(device_t dev, device_t child,
intrptr = intrmapptr = intrclrptr = 0; intrptr = intrmapptr = intrclrptr = 0;
intrmap = 0; intrmap = 0;
inr = INTVEC(vec); inr = INTVEC(vec);
if ((inr & INTMAP_OBIO) == 0) { if ((inr & INTMAP_OBIO_MASK) == 0) {
/* /*
* We're in an SBUS slot, register the map and clear * We're in an SBUS slot, register the map and clear
* intr registers. * intr registers.
@ -709,11 +710,10 @@ sbus_setup_intr(device_t dev, device_t child,
*/ */
SYSIO_WRITE8(sc, intrclrptr, 0); SYSIO_WRITE8(sc, intrclrptr, 0);
/* /*
* Enable the interrupt now we have the handler installed. * Enable the interrupt and program the target module now we have the
* Read the current value as we can't change it besides the * handler installed.
* valid bit so so make sure only this bit is changed.
*/ */
SYSIO_WRITE8(sc, intrmapptr, intrmap, PCPU_GET(mid)); SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid)));
return (error); return (error);
} }