For consistency within the front-end, prefer SDHCI_{READ,WRITE}_{2,4}()
to sdhci_acpi_{read,write}_{2,4}() in the sdhci_acpi_set_uhs_timing() added in r340543.
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parent
fe5e88fabf
commit
f5d03775e0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=340654
@ -203,7 +203,7 @@ sdhci_acpi_set_uhs_timing(device_t dev, struct sdhci_slot *slot)
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enum mmc_bus_timing timing;
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bus = slot->bus;
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old_timing = sdhci_acpi_read_2(bus, slot, SDHCI_HOST_CONTROL2);
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old_timing = SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2);
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old_timing &= SDHCI_CTRL2_UHS_MASK;
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sdhci_generic_set_uhs_timing(dev, slot);
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@ -220,19 +220,19 @@ sdhci_acpi_set_uhs_timing(device_t dev, struct sdhci_slot *slot)
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timing = ios->timing;
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if (old_timing == SDHCI_CTRL2_UHS_SDR104 &&
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timing == bus_timing_hs)
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sdhci_acpi_write_2(bus, slot, SDHCI_HOST_CONTROL2,
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sdhci_acpi_read_2(bus, slot, SDHCI_HOST_CONTROL2) &
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SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2,
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SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) &
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~SDHCI_CTRL2_SAMPLING_CLOCK);
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if (ios->clock > SD_SDR50_MAX &&
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old_timing != SDHCI_CTRL2_MMC_HS400 &&
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timing == bus_timing_mmc_hs400) {
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sdhci_acpi_write_2(bus, slot, SDHCI_HOST_CONTROL2,
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sdhci_acpi_read_2(bus, slot, SDHCI_HOST_CONTROL2) |
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SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2,
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SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) |
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SDHCI_CTRL2_SAMPLING_CLOCK);
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sdhci_acpi_write_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
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SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
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0x40003210);
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DELAY(20);
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sdhci_acpi_write_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
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SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG,
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0x40033210);
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}
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}
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