MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30 Add kernel side support for large TLB on BERI/CHERI. Modelled similar to NLM MFC after: 3 days Sponsored by: DAPRA/AFRL
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=256935
@ -80,6 +80,11 @@ OCTEON_VENDOR_RADISYS opt_cvmx.h
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OCTEON_VENDOR_GEFES opt_cvmx.h
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OCTEON_VENDOR_GEFES opt_cvmx.h
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OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
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OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
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#
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# Options specific to the BERI platform.
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#
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BERI_LARGE_TLB opt_global.h
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#
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#
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# Options that control the Atheros SoC peripherals
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# Options that control the Atheros SoC peripherals
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#
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#
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@ -2,3 +2,5 @@
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files "../beri/files.beri"
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files "../beri/files.beri"
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cpu CPU_MIPS4KC
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cpu CPU_MIPS4KC
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options BERI_LARGE_TLB
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@ -242,8 +242,13 @@ MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
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#ifdef CPU_CNMIPS
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#ifdef CPU_CNMIPS
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MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
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MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
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#endif
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#endif
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#ifdef CPU_NLM
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#ifdef BERI_LARGE_TLB
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MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
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#endif
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#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
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MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
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MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
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#endif
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#ifdef CPU_NLM
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MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
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MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
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#endif
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#endif
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MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
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MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
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@ -99,17 +99,29 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
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/* Learn TLB size and L1 cache geometry. */
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/* Learn TLB size and L1 cache geometry. */
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cfg1 = mips_rd_config1();
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cfg1 = mips_rd_config1();
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#ifndef CPU_NLM
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cpuinfo->tlb_nentries =
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#if defined(CPU_NLM)
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((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
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#else
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/* Account for Extended TLB entries in XLP */
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/* Account for Extended TLB entries in XLP */
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tmp = mips_rd_config6();
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tmp = mips_rd_config6();
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cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
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cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
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#elif defined(BERI_LARGE_TLB)
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/* Check if we support extended TLB entries and if so activate. */
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tmp = mips_rd_config5();
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#define BERI_CP5_LTLB_SUPPORTED 0x1
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if (tmp & BERI_CP5_LTLB_SUPPORTED) {
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/* See how many extra TLB entries we have. */
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tmp = mips_rd_config6();
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cpuinfo->tlb_nentries = (tmp >> 16) + 1;
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/* Activate the extended entries. */
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mips_wr_config6(tmp|0x4);
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} else
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#endif
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#if !defined(CPU_NLM)
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cpuinfo->tlb_nentries =
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((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
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#endif
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#endif
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/* Add extended TLB size information from config4. */
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#if defined(CPU_CNMIPS)
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#if defined(CPU_CNMIPS)
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/* Add extended TLB size information from config4. */
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cfg4 = mips_rd_config4();
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cfg4 = mips_rd_config4();
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if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
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if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
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cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;
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cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;
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@ -124,8 +136,8 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
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1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
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1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
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}
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}
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#ifndef CPU_CNMIPS
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/* L1 data cache. */
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/* L1 data cache. */
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#ifndef CPU_CNMIPS
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tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
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tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
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if (tmp != 0) {
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if (tmp != 0) {
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cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
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cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
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