A few improvements:
1. Define all registers. These definitions are needed to support
the FCM driver for direct-connect NAND.
2. Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus
attached device drivers. Use bus_space functions directly in the
lbc driver itself.
3. Be smarter about programming LAWs and mapping memory. The ranges
defined in the FDT are per bank (= chip select) and since we can
have up to 8 banks, we could easily use more than 8 LAWs or TLB
enrties when per-bank memory ranges need multiple LAWs or TLBs
due to alignment or size constraints.
We now combine all memory ranges into the fewest possible set of
contiguous regions and program the hardware for that. Thus, a
cleverly written FDT with 8 devices may still only need 1 LAW or
1 TLB entry. Note that the memory ranges can be assigned randomly
to the banks. We sort as we build to handle that.
4. Support the FCM when programming the OR register. This is mostly
for documention purposes as we do not have a way to define the
mode for a bank.
5. Remove Semihalf-ism: do not define DEBUG (only to undefine it
again).
This commit is contained in:
Marcel Moolenaar
parent
20b7961267
commit
f6703dd295
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=235937
@ -56,9 +56,6 @@ __FBSDID("$FreeBSD$");
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#include "ofw_bus_if.h"
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#include "lbc.h"
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#define DEBUG
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#undef DEBUG
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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@ -66,20 +63,6 @@ __FBSDID("$FreeBSD$");
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#define debugf(fmt, args...)
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#endif
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static __inline void
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lbc_write_reg(struct lbc_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
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}
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static __inline uint32_t
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lbc_read_reg(struct lbc_softc *sc, bus_size_t off)
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{
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return (bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
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}
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static MALLOC_DEFINE(M_LBC, "localbus", "localbus devices information");
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static int lbc_probe(device_t);
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@ -161,46 +144,123 @@ lbc_address_mask(uint32_t size)
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static void
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lbc_banks_unmap(struct lbc_softc *sc)
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{
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int i;
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int r;
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for (i = 0; i < LBC_DEV_MAX; i++) {
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if (sc->sc_banks[i].size == 0)
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continue;
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r = 0;
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while (r < LBC_DEV_MAX) {
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if (sc->sc_range[r].size == 0)
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return;
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law_disable(OCP85XX_TGTIF_LBC, sc->sc_banks[i].pa,
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sc->sc_banks[i].size);
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pmap_unmapdev(sc->sc_banks[i].va, sc->sc_banks[i].size);
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pmap_unmapdev(sc->sc_range[r].kva, sc->sc_range[r].size);
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law_disable(OCP85XX_TGTIF_LBC, sc->sc_range[r].addr,
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sc->sc_range[r].size);
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r++;
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}
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}
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static int
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lbc_banks_map(struct lbc_softc *sc)
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{
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u_long start, size;
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int error, i;
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vm_paddr_t end, start;
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vm_size_t size;
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u_int i, r, ranges, s;
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int error;
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bzero(sc->sc_range, sizeof(sc->sc_range));
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/*
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* Determine number of discontiguous address ranges to program.
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*/
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ranges = 0;
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for (i = 0; i < LBC_DEV_MAX; i++) {
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if (sc->sc_banks[i].size == 0)
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size = sc->sc_banks[i].size;
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if (size == 0)
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continue;
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/* Physical address start/size. */
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start = sc->sc_banks[i].pa;
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size = sc->sc_banks[i].size;
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start = sc->sc_banks[i].addr;
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for (r = 0; r < ranges; r++) {
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/* Avoid wrap-around bugs. */
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end = sc->sc_range[r].addr - 1 + sc->sc_range[r].size;
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if (start > 0 && end == start - 1) {
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sc->sc_range[r].size += size;
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break;
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}
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/* Avoid wrap-around bugs. */
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end = start - 1 + size;
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if (sc->sc_range[r].addr > 0 &&
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end == sc->sc_range[r].addr - 1) {
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sc->sc_range[r].addr = start;
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sc->sc_range[r].size += size;
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break;
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}
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}
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if (r == ranges) {
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/* New range; add using insertion sort */
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r = 0;
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while (r < ranges && sc->sc_range[r].addr < start)
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r++;
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for (s = ranges; s > r; s--)
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sc->sc_range[s] = sc->sc_range[s-1];
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sc->sc_range[r].addr = start;
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sc->sc_range[r].size = size;
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ranges++;
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}
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}
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/*
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* Configure LAW for this LBC bank (CS) and map its physical
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* memory region into KVA.
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*/
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/*
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* Ranges are sorted so quickly go over the list to merge ranges
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* that grew toward each other while building the ranges.
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*/
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r = 0;
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while (r < ranges - 1) {
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end = sc->sc_range[r].addr + sc->sc_range[r].size;
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if (end != sc->sc_range[r+1].addr) {
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r++;
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continue;
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}
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sc->sc_range[r].size += sc->sc_range[r+1].size;
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for (s = r + 1; s < ranges - 1; s++)
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sc->sc_range[s] = sc->sc_range[s+1];
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bzero(&sc->sc_range[s], sizeof(sc->sc_range[s]));
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ranges--;
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}
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/*
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* Configure LAW for the LBC ranges and map the physical memory
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* range into KVA.
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*/
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for (r = 0; r < ranges; r++) {
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start = sc->sc_range[r].addr;
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size = sc->sc_range[r].size;
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error = law_enable(OCP85XX_TGTIF_LBC, start, size);
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if (error)
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return (error);
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sc->sc_range[r].kva = (vm_offset_t)pmap_mapdev(start, size);
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}
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sc->sc_banks[i].va = (vm_offset_t)pmap_mapdev(start, size);
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if (sc->sc_banks[i].va == 0) {
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lbc_banks_unmap(sc);
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return (ENOSPC);
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/* XXX: need something better here? */
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if (ranges == 0)
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return (EINVAL);
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/* Assign KVA to banks based on the enclosing range. */
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for (i = 0; i < LBC_DEV_MAX; i++) {
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size = sc->sc_banks[i].size;
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if (size == 0)
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continue;
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start = sc->sc_banks[i].addr;
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for (r = 0; r < ranges; r++) {
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end = sc->sc_range[r].addr - 1 + sc->sc_range[r].size;
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if (start >= sc->sc_range[r].addr &&
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start - 1 + size <= end)
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break;
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}
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if (r < ranges) {
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sc->sc_banks[i].kva = sc->sc_range[r].kva +
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(start - sc->sc_range[r].addr);
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}
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}
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return (0);
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}
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@ -213,14 +273,18 @@ lbc_banks_enable(struct lbc_softc *sc)
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for (i = 0; i < LBC_DEV_MAX; i++) {
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size = sc->sc_banks[i].size;
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if (size == 0)
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if (size == 0) {
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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LBC85XX_BR(i), 0);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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LBC85XX_OR(i), 0);
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continue;
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}
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/*
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* Compute and program BR value.
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*/
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regval = 0;
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regval |= sc->sc_banks[i].pa;
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regval = sc->sc_banks[i].addr;
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switch (sc->sc_banks[i].width) {
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case 8:
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regval |= (1 << 11);
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@ -240,24 +304,22 @@ lbc_banks_enable(struct lbc_softc *sc)
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regval |= (sc->sc_banks[i].msel << 5);
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regval |= (sc->sc_banks[i].atom << 2);
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regval |= 1;
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lbc_write_reg(sc, LBC85XX_BR(i), regval);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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LBC85XX_BR(i), regval);
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/*
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* Compute and program OR value.
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*/
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regval = 0;
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regval |= lbc_address_mask(size);
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regval = lbc_address_mask(size);
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switch (sc->sc_banks[i].msel) {
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case LBCRES_MSEL_GPCM:
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/* TODO Add flag support for option registers */
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regval |= 0x00000ff7;
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regval |= 0x0ff7;
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break;
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case LBCRES_MSEL_FCM:
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printf("FCM mode not supported yet!");
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error = ENOSYS;
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goto fail;
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/* TODO Add flag support for options register */
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regval |= 0x0796;
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break;
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case LBCRES_MSEL_UPMA:
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case LBCRES_MSEL_UPMB:
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case LBCRES_MSEL_UPMC:
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@ -265,7 +327,8 @@ lbc_banks_enable(struct lbc_softc *sc)
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error = ENOSYS;
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goto fail;
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}
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lbc_write_reg(sc, LBC85XX_OR(i), regval);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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LBC85XX_OR(i), regval);
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}
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/*
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@ -276,7 +339,7 @@ lbc_banks_enable(struct lbc_softc *sc)
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* - set ECC parity type
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* - set bus monitor timing and timer prescale
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*/
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lbc_write_reg(sc, LBC85XX_LBCR, 0);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LBCR, 0);
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/*
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* Initialize clock ratio register:
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@ -284,8 +347,7 @@ lbc_banks_enable(struct lbc_softc *sc)
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* - configure LCLK delay cycles for the assertion of LALE
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* - set system clock divider
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*/
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lbc_write_reg(sc, LBC85XX_LCRR, 0x00030008);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LCRR, 0x00030008);
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return (0);
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fail:
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@ -348,7 +410,7 @@ fdt_lbc_reg_decode(phandle_t node, struct lbc_softc *sc,
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reg += addr_cells - 1 + size_cells;
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/* Calculate address range relative to VA base. */
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start = sc->sc_banks[bank].va + start;
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start = sc->sc_banks[bank].kva + start;
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end = start + count - 1;
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debugf("reg addr bank = %d, start = %lx, end = %lx, "
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@ -479,7 +541,7 @@ lbc_attach(device_t dev)
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debugf("bank = %d, start = %lx, size = %lx\n", bank,
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start, size);
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sc->sc_banks[bank].pa = start + offset;
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sc->sc_banks[bank].addr = start + offset;
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sc->sc_banks[bank].size = size;
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/*
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@ -676,3 +738,21 @@ lbc_get_devinfo(device_t bus, device_t child)
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di = device_get_ivars(child);
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return (&di->di_ofw);
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}
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void
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lbc_write_reg(device_t child, u_int off, uint32_t val)
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{
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struct lbc_softc *sc;
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sc = device_get_softc(device_get_parent(child));
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
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}
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uint32_t
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lbc_read_reg(device_t child, u_int off)
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{
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struct lbc_softc *sc;
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sc = device_get_softc(device_get_parent(child));
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return (bus_space_read_4(sc->sc_bst, sc->sc_bsh, off));
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}
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@ -33,10 +33,35 @@
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#define LBC_DEV_MAX 8
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/* Local access registers */
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#define LBC85XX_BR(n) (8 * n)
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#define LBC85XX_OR(n) (4 + (8 * n))
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#define LBC85XX_LBCR (0xd0)
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#define LBC85XX_LCRR (0xd4)
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#define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
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#define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
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#define LBC85XX_MAR 0x068 /* UPM address register */
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#define LBC85XX_MAMR 0x070 /* UPMA mode register */
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#define LBC85XX_MBMR 0x074 /* UPMB mode register */
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#define LBC85XX_MCMR 0x078 /* UPMC mode register */
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#define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */
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#define LBC85XX_MDR 0x088 /* UPM data register */
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#define LBC85XX_LSOR 0x090 /* Special operation initiation */
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#define LBC85XX_LURT 0x0a0 /* UPM refresh timer */
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#define LBC85XX_LSRT 0x0a4 /* SDRAM refresh timer */
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#define LBC85XX_LTESR 0x0b0 /* Transfer error status register */
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#define LBC85XX_LTEDR 0x0b4 /* Transfer error disable register */
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#define LBC85XX_LTEIR 0x0b8 /* Transfer error interrupt register */
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#define LBC85XX_LTEATR 0x0bc /* Transfer error attributes register */
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#define LBC85XX_LTEAR 0x0c0 /* Transfer error address register */
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#define LBC85XX_LTECCR 0x0c4 /* Transfer error ECC register */
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#define LBC85XX_LBCR 0x0d0 /* Configuration register */
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#define LBC85XX_LCRR 0x0d4 /* Clock ratio register */
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#define LBC85XX_FMR 0x0e0 /* Flash mode register */
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#define LBC85XX_FIR 0x0e4 /* Flash instruction register */
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#define LBC85XX_FCR 0x0e8 /* Flash command register */
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#define LBC85XX_FBAR 0x0ec /* Flash block address register */
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#define LBC85XX_FPAR 0x0f0 /* Flash page address register */
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#define LBC85XX_FBCR 0x0f4 /* Flash byte count register */
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#define LBC85XX_FECC0 0x100 /* Flash ECC block 0 register */
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#define LBC85XX_FECC1 0x104 /* Flash ECC block 0 register */
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#define LBC85XX_FECC2 0x108 /* Flash ECC block 0 register */
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#define LBC85XX_FECC3 0x10c /* Flash ECC block 0 register */
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/* LBC machine select */
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#define LBCRES_MSEL_GPCM 0
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@ -55,10 +80,16 @@
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#define LBCRES_ATOM_RAWA 1
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#define LBCRES_ATOM_WARA 2
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struct lbc_memrange {
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vm_paddr_t addr;
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vm_size_t size;
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vm_offset_t kva;
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};
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struct lbc_bank {
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u_long pa; /* physical addr of the bank */
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u_long size; /* bank size */
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vm_offset_t va; /* VA of the bank */
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vm_paddr_t addr; /* physical addr of the bank */
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vm_size_t size; /* bank size */
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vm_offset_t kva; /* VA of the bank */
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/*
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* XXX the following bank attributes do not have properties specified
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@ -84,6 +115,7 @@ struct lbc_softc {
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int sc_addr_cells;
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int sc_size_cells;
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struct lbc_memrange sc_range[LBC_DEV_MAX];
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struct lbc_bank sc_banks[LBC_DEV_MAX];
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};
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@ -93,4 +125,7 @@ struct lbc_devinfo {
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int di_bank;
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};
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uint32_t lbc_read_reg(device_t child, u_int off);
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void lbc_write_reg(device_t child, u_int off, uint32_t val);
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#endif /* _MACHINE_LBC_H_ */
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