Add support for the MIPS74K SoC family performance counters events.
These are similar to the mips24k performance counters - some are
available on perfcnt0/3, some are available on perfcnt1/4.
However, the events aren't all the same.
* Add the events, named the same as from Linux oprofile.
* Verify they're the same as "MIPS32(R) 74KTM Processor Core Family
Software User's Manual"; Document Number: MD00519; Revision 01.05.
* Rename INSTRUCTIONS to something else, so it doesn't clash with
the alias INSTRUCTIONS. I'll try to tidy this up later; there
are a few other aliases to add and shuffle around.
Tested:
* QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.)
* make universe; where it didn't fail for other reasons.
TODO:
* It'd be nice to support the four performance counters
in at least this hardware, rather than just two.
Reviewed by: bsdimp ("looks good; don't break world".)
This commit is contained in:
Adrian Chadd
parent
c4f9a74168
commit
f6e6460dfc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=281098
@ -159,6 +159,7 @@ PMC_CLASSDEP_TABLE(p6, P6);
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PMC_CLASSDEP_TABLE(xscale, XSCALE);
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PMC_CLASSDEP_TABLE(armv7, ARMV7);
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PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
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PMC_CLASSDEP_TABLE(mips74k, MIPS74K);
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PMC_CLASSDEP_TABLE(octeon, OCTEON);
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PMC_CLASSDEP_TABLE(ucf, UCF);
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PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
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@ -293,6 +294,7 @@ PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
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PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
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PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
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PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K);
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PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K);
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PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON);
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PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450);
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PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970);
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@ -360,6 +362,7 @@ PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7);
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#endif
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#if defined(__mips__)
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PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
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PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips);
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PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
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#endif /* __mips__ */
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#if defined(__powerpc__)
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@ -2432,6 +2435,13 @@ static struct pmc_event_alias mips24k_aliases[] = {
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EV_ALIAS(NULL, NULL)
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};
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static struct pmc_event_alias mips74k_aliases[] = {
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EV_ALIAS("instructions", "INSTR_EXECUTED"),
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EV_ALIAS("branches", "BRANCH_INSNS"),
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EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"),
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EV_ALIAS(NULL, NULL)
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};
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static struct pmc_event_alias octeon_aliases[] = {
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EV_ALIAS("instructions", "RET"),
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EV_ALIAS("branches", "BR"),
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@ -2923,6 +2933,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
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ev = mips24k_event_table;
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count = PMC_EVENT_TABLE_SIZE(mips24k);
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break;
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case PMC_CLASS_MIPS74K:
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ev = mips74k_event_table;
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count = PMC_EVENT_TABLE_SIZE(mips74k);
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break;
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case PMC_CLASS_OCTEON:
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ev = octeon_event_table;
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count = PMC_EVENT_TABLE_SIZE(octeon);
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@ -3213,6 +3227,10 @@ pmc_init(void)
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PMC_MDEP_INIT(mips24k);
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pmc_class_table[n] = &mips24k_class_table_descr;
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break;
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case PMC_CPU_MIPS_74K:
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PMC_MDEP_INIT(mips74k);
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pmc_class_table[n] = &mips74k_class_table_descr;
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break;
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case PMC_CPU_MIPS_OCTEON:
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PMC_MDEP_INIT(octeon);
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pmc_class_table[n] = &octeon_class_table_descr;
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@ -3414,6 +3432,9 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
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} else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
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ev = mips24k_event_table;
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evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
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} else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) {
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ev = mips74k_event_table;
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evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k);
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} else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
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ev = octeon_event_table;
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evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
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@ -89,3 +89,4 @@ dev/nvram2env/nvram2env.c optional nvram2env
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# hwpmc support
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dev/hwpmc/hwpmc_mips.c optional hwpmc
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dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k
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dev/hwpmc/hwpmc_mips74k.c optional hwpmc_mips74k
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261
sys/dev/hwpmc/hwpmc_mips74k.c
Normal file
261
sys/dev/hwpmc/hwpmc_mips74k.c
Normal file
@ -0,0 +1,261 @@
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/*-
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* Copyright (c) 2010 George V. Neville-Neil <gnn@freebsd.org>
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* Copyright (c) 2015 Adrian Chadd <adrian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/pmc_mdep.h>
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#define MIPS74K_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
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PMC_CAP_THRESHOLD | PMC_CAP_READ | \
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PMC_CAP_WRITE | PMC_CAP_INVERT | \
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PMC_CAP_QUALIFIER)
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/* 0x1 - Exception_enable */
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#define MIPS74K_PMC_INTERRUPT_ENABLE 0x10 /* Enable interrupts */
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#define MIPS74K_PMC_USER_ENABLE 0x08 /* Count in USER mode */
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#define MIPS74K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */
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#define MIPS74K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */
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#define MIPS74K_PMC_ENABLE (MIPS74K_PMC_USER_ENABLE | \
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MIPS74K_PMC_SUPER_ENABLE | \
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MIPS74K_PMC_KERNEL_ENABLE)
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#define MIPS74K_PMC_SELECT 5 /* Which bit position the event starts at. */
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const struct mips_event_code_map mips_event_codes[] = {
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{ PMC_EV_MIPS74K_CYCLES, MIPS_CTR_ALL, 0 },
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{ PMC_EV_MIPS74K_INSTR_EXECUTED, MIPS_CTR_ALL, 1 },
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{ PMC_EV_MIPS74K_PREDICTED_JR_31, MIPS_CTR_0, 2 },
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{ PMC_EV_MIPS74K_JR_31_MISPREDICTIONS, MIPS_CTR_1, 2 },
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{ PMC_EV_MIPS74K_REDIRECT_STALLS, MIPS_CTR_0, 3 },
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{ PMC_EV_MIPS74K_JR_31_NO_PREDICTIONS, MIPS_CTR_1, 3 },
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{ PMC_EV_MIPS74K_ITLB_ACCESSES, MIPS_CTR_0, 4 },
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{ PMC_EV_MIPS74K_ITLB_MISSES, MIPS_CTR_1, 4 },
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{ PMC_EV_MIPS74K_JTLB_INSN_MISSES, MIPS_CTR_1, 5 },
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{ PMC_EV_MIPS74K_ICACHE_ACCESSES, MIPS_CTR_0, 6 },
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{ PMC_EV_MIPS74K_ICACHE_MISSES, MIPS_CTR_1, 6 },
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{ PMC_EV_MIPS74K_ICACHE_MISS_STALLS, MIPS_CTR_0, 7 },
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{ PMC_EV_MIPS74K_UNCACHED_IFETCH_STALLS, MIPS_CTR_0, 8 },
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{ PMC_EV_MIPS74K_PDTRACE_BACK_STALLS, MIPS_CTR_1, 8 },
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{ PMC_EV_MIPS74K_IFU_REPLAYS, MIPS_CTR_0, 9 },
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{ PMC_EV_MIPS74K_KILLED_FETCH_SLOTS, MIPS_CTR_1, 9 },
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{ PMC_EV_MIPS74K_IFU_IDU_MISS_PRED_UPSTREAM_CYCLES, MIPS_CTR_0, 11 },
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{ PMC_EV_MIPS74K_IFU_IDU_NO_FETCH_CYCLES, MIPS_CTR_1, 11 },
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{ PMC_EV_MIPS74K_IFU_IDU_CLOGED_DOWNSTREAM_CYCLES, MIPS_CTR_0, 12 },
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{ PMC_EV_MIPS74K_DDQ0_FULL_DR_STALLS, MIPS_CTR_0, 13 },
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{ PMC_EV_MIPS74K_DDQ1_FULL_DR_STALLS, MIPS_CTR_1, 13 },
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{ PMC_EV_MIPS74K_ALCB_FULL_DR_STALLS, MIPS_CTR_0, 14 },
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{ PMC_EV_MIPS74K_AGCB_FULL_DR_STALLS, MIPS_CTR_1, 14 },
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{ PMC_EV_MIPS74K_CLDQ_FULL_DR_STALLS, MIPS_CTR_0, 15 },
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{ PMC_EV_MIPS74K_IODQ_FULL_DR_STALLS, MIPS_CTR_1, 15 },
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{ PMC_EV_MIPS74K_ALU_EMPTY_CYCLES, MIPS_CTR_0, 16 },
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{ PMC_EV_MIPS74K_AGEN_EMPTY_CYCLES, MIPS_CTR_1, 16 },
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{ PMC_EV_MIPS74K_ALU_OPERANDS_NOT_READY_CYCLES, MIPS_CTR_0, 17 },
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{ PMC_EV_MIPS74K_AGEN_OPERANDS_NOT_READY_CYCLES, MIPS_CTR_1, 17 },
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{ PMC_EV_MIPS74K_ALU_NO_ISSUES_CYCLES, MIPS_CTR_0, 18 },
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{ PMC_EV_MIPS74K_AGEN_NO_ISSUES_CYCLES, MIPS_CTR_1, 18 },
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{ PMC_EV_MIPS74K_ALU_BUBBLE_CYCLES, MIPS_CTR_0, 19 },
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{ PMC_EV_MIPS74K_AGEN_BUBBLE_CYCLES, MIPS_CTR_1, 19 },
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{ PMC_EV_MIPS74K_SINGLE_ISSUE_CYCLES, MIPS_CTR_0, 20 },
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{ PMC_EV_MIPS74K_DUAL_ISSUE_CYCLES, MIPS_CTR_1, 20 },
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{ PMC_EV_MIPS74K_OOO_ALU_ISSUE_CYCLES, MIPS_CTR_0, 21 },
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{ PMC_EV_MIPS74K_OOO_AGEN_ISSUE_CYCLES, MIPS_CTR_1, 21 },
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{ PMC_EV_MIPS74K_JALR_JALR_HB_INSNS, MIPS_CTR_0, 22 },
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{ PMC_EV_MIPS74K_DCACHE_LINE_REFILL_REQUESTS, MIPS_CTR_1, 22 },
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{ PMC_EV_MIPS74K_DCACHE_LOAD_ACCESSES, MIPS_CTR_0, 23 },
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{ PMC_EV_MIPS74K_DCACHE_ACCESSES, MIPS_CTR_1, 23 },
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{ PMC_EV_MIPS74K_DCACHE_WRITEBACKS, MIPS_CTR_0, 24 },
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{ PMC_EV_MIPS74K_DCACHE_MISSES, MIPS_CTR_1, 24 },
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{ PMC_EV_MIPS74K_JTLB_DATA_ACCESSES, MIPS_CTR_0, 25 },
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{ PMC_EV_MIPS74K_JTLB_DATA_MISSES, MIPS_CTR_1, 25 },
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{ PMC_EV_MIPS74K_LOAD_STORE_REPLAYS, MIPS_CTR_0, 26 },
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{ PMC_EV_MIPS74K_VA_TRANSALTION_CORNER_CASES, MIPS_CTR_1, 26 },
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{ PMC_EV_MIPS74K_LOAD_STORE_BLOCKED_CYCLES, MIPS_CTR_0, 27 },
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{ PMC_EV_MIPS74K_LOAD_STORE_NO_FILL_REQUESTS, MIPS_CTR_1, 27 },
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{ PMC_EV_MIPS74K_L2_CACHE_WRITEBACKS, MIPS_CTR_0, 28 },
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{ PMC_EV_MIPS74K_L2_CACHE_ACCESSES, MIPS_CTR_1, 28 },
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{ PMC_EV_MIPS74K_L2_CACHE_MISSES, MIPS_CTR_0, 29 },
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{ PMC_EV_MIPS74K_L2_CACHE_MISS_CYCLES, MIPS_CTR_1, 29 },
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{ PMC_EV_MIPS74K_FSB_FULL_STALLS, MIPS_CTR_0, 30 },
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{ PMC_EV_MIPS74K_FSB_OVER_50_FULL, MIPS_CTR_1, 30 },
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{ PMC_EV_MIPS74K_LDQ_FULL_STALLS, MIPS_CTR_0, 31 },
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{ PMC_EV_MIPS74K_LDQ_OVER_50_FULL, MIPS_CTR_1, 31 },
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{ PMC_EV_MIPS74K_WBB_FULL_STALLS, MIPS_CTR_0, 32 },
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{ PMC_EV_MIPS74K_WBB_OVER_50_FULL, MIPS_CTR_1, 32 },
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{ PMC_EV_MIPS74K_LOAD_MISS_CONSUMER_REPLAYS, MIPS_CTR_0, 35 },
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{ PMC_EV_MIPS74K_CP1_CP2_LOAD_INSNS, MIPS_CTR_1, 35 },
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{ PMC_EV_MIPS74K_JR_NON_31_INSNS, MIPS_CTR_0, 36 },
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{ PMC_EV_MIPS74K_MISPREDICTED_JR_31_INSNS, MIPS_CTR_1, 36 },
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{ PMC_EV_MIPS74K_BRANCH_INSNS, MIPS_CTR_0, 37 },
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{ PMC_EV_MIPS74K_CP1_CP2_COND_BRANCH_INSNS, MIPS_CTR_1, 37 },
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{ PMC_EV_MIPS74K_BRANCH_LIKELY_INSNS, MIPS_CTR_0, 38 },
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{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_LIKELY_INSNS, MIPS_CTR_1, 38 },
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{ PMC_EV_MIPS74K_COND_BRANCH_INSNS, MIPS_CTR_0, 39 },
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{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS, MIPS_CTR_1, 39 },
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{ PMC_EV_MIPS74K_INTEGER_INSNS, MIPS_CTR_0, 40 },
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{ PMC_EV_MIPS74K_FPU_INSNS, MIPS_CTR_1, 40 },
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{ PMC_EV_MIPS74K_LOAD_INSNS, MIPS_CTR_0, 41 },
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{ PMC_EV_MIPS74K_STORE_INSNS, MIPS_CTR_1, 41 },
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{ PMC_EV_MIPS74K_J_JAL_INSNS, MIPS_CTR_0, 42 },
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{ PMC_EV_MIPS74K_MIPS16_INSNS, MIPS_CTR_1, 42 },
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{ PMC_EV_MIPS74K_NOP_INSNS, MIPS_CTR_0, 43 },
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{ PMC_EV_MIPS74K_NT_MUL_DIV_INSNS, MIPS_CTR_1, 43 },
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{ PMC_EV_MIPS74K_DSP_INSNS, MIPS_CTR_0, 44 },
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{ PMC_EV_MIPS74K_ALU_DSP_SATURATION_INSNS, MIPS_CTR_1, 44 },
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{ PMC_EV_MIPS74K_DSP_BRANCH_INSNS, MIPS_CTR_0, 45 },
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{ PMC_EV_MIPS74K_MDU_DSP_SATURATION_INSNS, MIPS_CTR_1, 45 },
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{ PMC_EV_MIPS74K_UNCACHED_LOAD_INSNS, MIPS_CTR_0, 46 },
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{ PMC_EV_MIPS74K_UNCACHED_STORE_INSNS, MIPS_CTR_1, 46 },
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{ PMC_EV_MIPS74K_EJTAG_INSN_TRIGGERS, MIPS_CTR_0, 49 },
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{ PMC_EV_MIPS74K_CP1_BRANCH_MISPREDICTIONS, MIPS_CTR_0, 50 },
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{ PMC_EV_MIPS74K_SC_INSNS, MIPS_CTR_0, 51 },
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{ PMC_EV_MIPS74K_FAILED_SC_INSNS, MIPS_CTR_1, 51 },
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{ PMC_EV_MIPS74K_PREFETCH_INSNS, MIPS_CTR_0, 52 },
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{ PMC_EV_MIPS74K_CACHE_HIT_PREFETCH_INSNS, MIPS_CTR_1, 52 },
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{ PMC_EV_MIPS74K_NO_INSN_CYCLES, MIPS_CTR_0, 53 },
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{ PMC_EV_MIPS74K_LOAD_MISS_INSNS, MIPS_CTR_1, 53 },
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{ PMC_EV_MIPS74K_ONE_INSN_CYCLES, MIPS_CTR_0, 54 },
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{ PMC_EV_MIPS74K_TWO_INSNS_CYCLES, MIPS_CTR_1, 54 },
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{ PMC_EV_MIPS74K_GFIFO_BLOCKED_CYCLES, MIPS_CTR_0, 55 },
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{ PMC_EV_MIPS74K_CP1_CP2_STORE_INSNS, MIPS_CTR_1, 55 },
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{ PMC_EV_MIPS74K_MISPREDICTION_STALLS, MIPS_CTR_0, 56 },
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{ PMC_EV_MIPS74K_MISPREDICTED_BRANCH_INSNS_CYCLES, MIPS_CTR_0, 57 },
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{ PMC_EV_MIPS74K_EXCEPTIONS_TAKEN, MIPS_CTR_0, 58 },
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{ PMC_EV_MIPS74K_GRADUATION_REPLAYS, MIPS_CTR_1, 58 },
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{ PMC_EV_MIPS74K_COREEXTEND_EVENTS, MIPS_CTR_0, 59 },
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{ PMC_EV_MIPS74K_ISPRAM_EVENTS, MIPS_CTR_0, 62 },
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{ PMC_EV_MIPS74K_DSPRAM_EVENTS, MIPS_CTR_1, 62 },
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{ PMC_EV_MIPS74K_L2_CACHE_SINGLE_BIT_ERRORS, MIPS_CTR_0, 63 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_0, MIPS_CTR_0, 64 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_1, MIPS_CTR_1, 64 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_2, MIPS_CTR_0, 65 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_3, MIPS_CTR_1, 65 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_4, MIPS_CTR_0, 66 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_5, MIPS_CTR_1, 66 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_6, MIPS_CTR_0, 67 },
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{ PMC_EV_MIPS74K_SYSTEM_EVENT_7, MIPS_CTR_1, 67 },
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{ PMC_EV_MIPS74K_OCP_ALL_REQUESTS, MIPS_CTR_0, 68 },
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{ PMC_EV_MIPS74K_OCP_ALL_CACHEABLE_REQUESTS, MIPS_CTR_1, 68 },
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{ PMC_EV_MIPS74K_OCP_READ_REQUESTS, MIPS_CTR_0, 69 },
|
||||
{ PMC_EV_MIPS74K_OCP_READ_CACHEABLE_REQUESTS, MIPS_CTR_1, 69 },
|
||||
{ PMC_EV_MIPS74K_OCP_WRITE_REQUESTS, MIPS_CTR_0, 70 },
|
||||
{ PMC_EV_MIPS74K_OCP_WRITE_CACHEABLE_REQUESTS, MIPS_CTR_1, 70 },
|
||||
{ PMC_EV_MIPS74K_FSB_LESS_25_FULL, MIPS_CTR_0, 74 },
|
||||
{ PMC_EV_MIPS74K_FSB_25_50_FULL, MIPS_CTR_1, 74 },
|
||||
{ PMC_EV_MIPS74K_LDQ_LESS_25_FULL, MIPS_CTR_0, 75 },
|
||||
{ PMC_EV_MIPS74K_LDQ_25_50_FULL, MIPS_CTR_1, 75 },
|
||||
{ PMC_EV_MIPS74K_WBB_LESS_25_FULL, MIPS_CTR_0, 76 },
|
||||
{ PMC_EV_MIPS74K_WBB_25_50_FULL, MIPS_CTR_1, 76 },
|
||||
};
|
||||
|
||||
const int mips_event_codes_size =
|
||||
sizeof(mips_event_codes) / sizeof(mips_event_codes[0]);
|
||||
|
||||
struct mips_pmc_spec mips_pmc_spec = {
|
||||
.ps_cpuclass = PMC_CLASS_MIPS74K,
|
||||
.ps_cputype = PMC_CPU_MIPS_74K,
|
||||
.ps_capabilities = MIPS74K_PMC_CAPS,
|
||||
.ps_counter_width = 32
|
||||
};
|
||||
|
||||
/*
|
||||
* Performance Count Register N
|
||||
*/
|
||||
uint64_t
|
||||
mips_pmcn_read(unsigned int pmc)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips74k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
/* The counter value is the next value after the control register. */
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
reg = mips_rd_perfcnt1();
|
||||
break;
|
||||
case 1:
|
||||
reg = mips_rd_perfcnt3();
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint64_t
|
||||
mips_pmcn_write(unsigned int pmc, uint64_t reg)
|
||||
{
|
||||
|
||||
KASSERT(pmc < mips_npmcs, ("[mips74k,%d] illegal PMC number %d",
|
||||
__LINE__, pmc));
|
||||
|
||||
switch (pmc) {
|
||||
case 0:
|
||||
mips_wr_perfcnt1(reg);
|
||||
break;
|
||||
case 1:
|
||||
mips_wr_perfcnt3(reg);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return (reg);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
|
||||
{
|
||||
uint32_t config;
|
||||
|
||||
config = event;
|
||||
|
||||
config <<= MIPS74K_PMC_SELECT;
|
||||
|
||||
if (caps & PMC_CAP_SYSTEM)
|
||||
config |= (MIPS74K_PMC_SUPER_ENABLE |
|
||||
MIPS74K_PMC_KERNEL_ENABLE);
|
||||
if (caps & PMC_CAP_USER)
|
||||
config |= MIPS74K_PMC_USER_ENABLE;
|
||||
if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
|
||||
config |= MIPS74K_PMC_ENABLE;
|
||||
if (caps & PMC_CAP_INTERRUPT)
|
||||
config |= MIPS74K_PMC_INTERRUPT_ENABLE;
|
||||
|
||||
PMCDBG(MDP,ALL,2,"mips74k-get_perfctl ri=%d -> config=0x%x", ri, config);
|
||||
|
||||
return (config);
|
||||
}
|
||||
@ -4892,6 +4892,138 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
|
||||
#define PMC_EV_MIPS24K_FIRST PMC_EV_MIPS24K_CYCLE
|
||||
#define PMC_EV_MIPS24K_LAST PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS
|
||||
|
||||
/*
|
||||
* MIPS74k events. Similar to MIPS24k, the arrangement
|
||||
* is (0,2) then (1,3) events.
|
||||
*/
|
||||
#define __PMC_EV_MIPS74K() \
|
||||
__PMC_EV(MIPS74K, CYCLES) \
|
||||
__PMC_EV(MIPS74K, INSTR_EXECUTED) \
|
||||
__PMC_EV(MIPS74K, PREDICTED_JR_31) \
|
||||
__PMC_EV(MIPS74K, JR_31_MISPREDICTIONS) \
|
||||
__PMC_EV(MIPS74K, REDIRECT_STALLS) \
|
||||
__PMC_EV(MIPS74K, JR_31_NO_PREDICTIONS) \
|
||||
__PMC_EV(MIPS74K, ITLB_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, ITLB_MISSES) \
|
||||
__PMC_EV(MIPS74K, JTLB_INSN_MISSES) \
|
||||
__PMC_EV(MIPS74K, ICACHE_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, ICACHE_MISSES) \
|
||||
__PMC_EV(MIPS74K, ICACHE_MISS_STALLS) \
|
||||
__PMC_EV(MIPS74K, UNCACHED_IFETCH_STALLS) \
|
||||
__PMC_EV(MIPS74K, PDTRACE_BACK_STALLS) \
|
||||
__PMC_EV(MIPS74K, IFU_REPLAYS) \
|
||||
__PMC_EV(MIPS74K, KILLED_FETCH_SLOTS) \
|
||||
__PMC_EV(MIPS74K, IFU_IDU_MISS_PRED_UPSTREAM_CYCLES) \
|
||||
__PMC_EV(MIPS74K, IFU_IDU_NO_FETCH_CYCLES) \
|
||||
__PMC_EV(MIPS74K, IFU_IDU_CLOGED_DOWNSTREAM_CYCLES) \
|
||||
__PMC_EV(MIPS74K, DDQ0_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, DDQ1_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, ALCB_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, AGCB_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, CLDQ_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, IODQ_FULL_DR_STALLS) \
|
||||
__PMC_EV(MIPS74K, ALU_EMPTY_CYCLES) \
|
||||
__PMC_EV(MIPS74K, AGEN_EMPTY_CYCLES) \
|
||||
__PMC_EV(MIPS74K, ALU_OPERANDS_NOT_READY_CYCLES) \
|
||||
__PMC_EV(MIPS74K, AGEN_OPERANDS_NOT_READY_CYCLES) \
|
||||
__PMC_EV(MIPS74K, ALU_NO_ISSUES_CYCLES) \
|
||||
__PMC_EV(MIPS74K, AGEN_NO_ISSUES_CYCLES) \
|
||||
__PMC_EV(MIPS74K, ALU_BUBBLE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, AGEN_BUBBLE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, SINGLE_ISSUE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, DUAL_ISSUE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, OOO_ALU_ISSUE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, OOO_AGEN_ISSUE_CYCLES) \
|
||||
__PMC_EV(MIPS74K, JALR_JALR_HB_INSNS) \
|
||||
__PMC_EV(MIPS74K, DCACHE_LINE_REFILL_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, DCACHE_LOAD_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, DCACHE_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, DCACHE_WRITEBACKS) \
|
||||
__PMC_EV(MIPS74K, DCACHE_MISSES) \
|
||||
__PMC_EV(MIPS74K, JTLB_DATA_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, JTLB_DATA_MISSES) \
|
||||
__PMC_EV(MIPS74K, LOAD_STORE_REPLAYS) \
|
||||
__PMC_EV(MIPS74K, VA_TRANSALTION_CORNER_CASES) \
|
||||
__PMC_EV(MIPS74K, LOAD_STORE_BLOCKED_CYCLES) \
|
||||
__PMC_EV(MIPS74K, LOAD_STORE_NO_FILL_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, L2_CACHE_WRITEBACKS) \
|
||||
__PMC_EV(MIPS74K, L2_CACHE_ACCESSES) \
|
||||
__PMC_EV(MIPS74K, L2_CACHE_MISSES) \
|
||||
__PMC_EV(MIPS74K, L2_CACHE_MISS_CYCLES) \
|
||||
__PMC_EV(MIPS74K, FSB_FULL_STALLS) \
|
||||
__PMC_EV(MIPS74K, FSB_OVER_50_FULL) \
|
||||
__PMC_EV(MIPS74K, LDQ_FULL_STALLS) \
|
||||
__PMC_EV(MIPS74K, LDQ_OVER_50_FULL) \
|
||||
__PMC_EV(MIPS74K, WBB_FULL_STALLS) \
|
||||
__PMC_EV(MIPS74K, WBB_OVER_50_FULL) \
|
||||
__PMC_EV(MIPS74K, LOAD_MISS_CONSUMER_REPLAYS) \
|
||||
__PMC_EV(MIPS74K, CP1_CP2_LOAD_INSNS) \
|
||||
__PMC_EV(MIPS74K, JR_NON_31_INSNS) \
|
||||
__PMC_EV(MIPS74K, MISPREDICTED_JR_31_INSNS) \
|
||||
__PMC_EV(MIPS74K, BRANCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, CP1_CP2_COND_BRANCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, BRANCH_LIKELY_INSNS) \
|
||||
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_LIKELY_INSNS) \
|
||||
__PMC_EV(MIPS74K, COND_BRANCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, INTEGER_INSNS) \
|
||||
__PMC_EV(MIPS74K, FPU_INSNS) \
|
||||
__PMC_EV(MIPS74K, LOAD_INSNS) \
|
||||
__PMC_EV(MIPS74K, STORE_INSNS) \
|
||||
__PMC_EV(MIPS74K, J_JAL_INSNS) \
|
||||
__PMC_EV(MIPS74K, MIPS16_INSNS) \
|
||||
__PMC_EV(MIPS74K, NOP_INSNS) \
|
||||
__PMC_EV(MIPS74K, NT_MUL_DIV_INSNS) \
|
||||
__PMC_EV(MIPS74K, DSP_INSNS) \
|
||||
__PMC_EV(MIPS74K, ALU_DSP_SATURATION_INSNS) \
|
||||
__PMC_EV(MIPS74K, DSP_BRANCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, MDU_DSP_SATURATION_INSNS) \
|
||||
__PMC_EV(MIPS74K, UNCACHED_LOAD_INSNS) \
|
||||
__PMC_EV(MIPS74K, UNCACHED_STORE_INSNS) \
|
||||
__PMC_EV(MIPS74K, EJTAG_INSN_TRIGGERS) \
|
||||
__PMC_EV(MIPS74K, CP1_BRANCH_MISPREDICTIONS) \
|
||||
__PMC_EV(MIPS74K, SC_INSNS) \
|
||||
__PMC_EV(MIPS74K, FAILED_SC_INSNS) \
|
||||
__PMC_EV(MIPS74K, PREFETCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, CACHE_HIT_PREFETCH_INSNS) \
|
||||
__PMC_EV(MIPS74K, NO_INSN_CYCLES) \
|
||||
__PMC_EV(MIPS74K, LOAD_MISS_INSNS) \
|
||||
__PMC_EV(MIPS74K, ONE_INSN_CYCLES) \
|
||||
__PMC_EV(MIPS74K, TWO_INSNS_CYCLES) \
|
||||
__PMC_EV(MIPS74K, GFIFO_BLOCKED_CYCLES) \
|
||||
__PMC_EV(MIPS74K, CP1_CP2_STORE_INSNS) \
|
||||
__PMC_EV(MIPS74K, MISPREDICTION_STALLS) \
|
||||
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS_CYCLES) \
|
||||
__PMC_EV(MIPS74K, EXCEPTIONS_TAKEN) \
|
||||
__PMC_EV(MIPS74K, GRADUATION_REPLAYS) \
|
||||
__PMC_EV(MIPS74K, COREEXTEND_EVENTS) \
|
||||
__PMC_EV(MIPS74K, ISPRAM_EVENTS) \
|
||||
__PMC_EV(MIPS74K, DSPRAM_EVENTS) \
|
||||
__PMC_EV(MIPS74K, L2_CACHE_SINGLE_BIT_ERRORS) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_0) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_1) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_2) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_3) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_4) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_5) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_6) \
|
||||
__PMC_EV(MIPS74K, SYSTEM_EVENT_7) \
|
||||
__PMC_EV(MIPS74K, OCP_ALL_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, OCP_ALL_CACHEABLE_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, OCP_READ_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, OCP_READ_CACHEABLE_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, OCP_WRITE_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, OCP_WRITE_CACHEABLE_REQUESTS) \
|
||||
__PMC_EV(MIPS74K, FSB_LESS_25_FULL) \
|
||||
__PMC_EV(MIPS74K, FSB_25_50_FULL) \
|
||||
__PMC_EV(MIPS74K, LDQ_LESS_25_FULL) \
|
||||
__PMC_EV(MIPS74K, LDQ_25_50_FULL) \
|
||||
__PMC_EV(MIPS74K, WBB_LESS_25_FULL) \
|
||||
__PMC_EV(MIPS74K, WBB_25_50_FULL)
|
||||
|
||||
#define PMC_EV_MIPS74K_FIRST PMC_EV_MIPS74K_CYCLES
|
||||
#define PMC_EV_MIPS74K_LAST PMC_EV_MIPS74K_WBB_25_50_FULL
|
||||
|
||||
/*
|
||||
* Cavium Octeon counters. Obtained from cvmx-core.h
|
||||
*/
|
||||
@ -5256,6 +5388,8 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
|
||||
* 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
|
||||
* 0x11200 0x00FF INTEL XScale events
|
||||
* 0x11300 0x00FF MIPS 24K events
|
||||
* 0x11400 0x00FF Octeon events
|
||||
* 0x11500 0x00FF MIPS 74K events
|
||||
* 0x14000 0x0100 ARMv7 events
|
||||
* 0x20000 0x1000 Software events
|
||||
*/
|
||||
@ -5282,6 +5416,8 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
|
||||
__PMC_EV_MIPS24K() \
|
||||
__PMC_EV_BLOCK(OCTEON, 0x11400) \
|
||||
__PMC_EV_OCTEON() \
|
||||
__PMC_EV_BLOCK(MIPS74K, 0x11500) \
|
||||
__PMC_EV_MIPS74K() \
|
||||
__PMC_EV_BLOCK(UCF, 0x12000) \
|
||||
__PMC_EV_UCF() \
|
||||
__PMC_EV_BLOCK(UCP, 0x12080) \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user