Fix style(9) space vs tab.
Reviewed by: jhb MFC after: 3 weeks. Sponsored by: iXsystems Inc. Differential Revision: https://reviews.freebsd.org/D15768
This commit is contained in:
Marcelo Araujo
parent
23fe789d78
commit
f7224b709f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=335104
@ -885,7 +885,7 @@ basl_make_templates(void)
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int len;
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err = 0;
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/*
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*
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*/
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@ -33,292 +33,292 @@
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#define _AHCI_H_
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/* ATA register defines */
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#define ATA_DATA 0 /* (RW) data */
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#define ATA_DATA 0 /* (RW) data */
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#define ATA_FEATURE 1 /* (W) feature */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_FEATURE 1 /* (W) feature */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 2 /* (W) sector count */
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#define ATA_COUNT 2 /* (W) sector count */
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#define ATA_SECTOR 3 /* (RW) sector # */
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#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
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#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
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#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
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#define ATA_D_LBA 0x40 /* use LBA addressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_SECTOR 3 /* (RW) sector # */
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#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
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#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
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#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
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#define ATA_D_LBA 0x40 /* use LBA addressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_COMMAND 7 /* (W) command */
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#define ATA_COMMAND 7 /* (W) command */
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#define ATA_ERROR 8 /* (R) error */
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#define ATA_E_ILI 0x01 /* illegal length */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
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#define ATA_ERROR 8 /* (R) error */
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#define ATA_E_ILI 0x01 /* illegal length */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
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#define ATA_IREASON 9 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_IREASON 9 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_STATUS 10 /* (R) status */
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#define ATA_ALTSTAT 11 /* (R) alternate status */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_STATUS 10 /* (R) status */
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#define ATA_ALTSTAT 11 /* (R) alternate status */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_CONTROL 12 /* (W) control */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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#define ATA_A_HOB 0x80 /* High Order Byte enable */
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#define ATA_CONTROL 12 /* (W) control */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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#define ATA_A_HOB 0x80 /* High Order Byte enable */
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/* SATA register defines */
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#define ATA_SSTATUS 13
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#define ATA_SS_DET_MASK 0x0000000f
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#define ATA_SS_DET_NO_DEVICE 0x00000000
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#define ATA_SS_DET_DEV_PRESENT 0x00000001
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#define ATA_SS_DET_PHY_ONLINE 0x00000003
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#define ATA_SS_DET_PHY_OFFLINE 0x00000004
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#define ATA_SSTATUS 13
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#define ATA_SS_DET_MASK 0x0000000f
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#define ATA_SS_DET_NO_DEVICE 0x00000000
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#define ATA_SS_DET_DEV_PRESENT 0x00000001
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#define ATA_SS_DET_PHY_ONLINE 0x00000003
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#define ATA_SS_DET_PHY_OFFLINE 0x00000004
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#define ATA_SS_SPD_MASK 0x000000f0
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#define ATA_SS_SPD_NO_SPEED 0x00000000
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#define ATA_SS_SPD_GEN1 0x00000010
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#define ATA_SS_SPD_GEN2 0x00000020
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#define ATA_SS_SPD_GEN3 0x00000030
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#define ATA_SS_SPD_MASK 0x000000f0
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#define ATA_SS_SPD_NO_SPEED 0x00000000
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#define ATA_SS_SPD_GEN1 0x00000010
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#define ATA_SS_SPD_GEN2 0x00000020
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#define ATA_SS_SPD_GEN3 0x00000030
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#define ATA_SS_IPM_MASK 0x00000f00
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#define ATA_SS_IPM_NO_DEVICE 0x00000000
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#define ATA_SS_IPM_ACTIVE 0x00000100
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#define ATA_SS_IPM_PARTIAL 0x00000200
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#define ATA_SS_IPM_SLUMBER 0x00000600
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#define ATA_SS_IPM_DEVSLEEP 0x00000800
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#define ATA_SS_IPM_MASK 0x00000f00
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#define ATA_SS_IPM_NO_DEVICE 0x00000000
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#define ATA_SS_IPM_ACTIVE 0x00000100
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#define ATA_SS_IPM_PARTIAL 0x00000200
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#define ATA_SS_IPM_SLUMBER 0x00000600
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#define ATA_SS_IPM_DEVSLEEP 0x00000800
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#define ATA_SERROR 14
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#define ATA_SE_DATA_CORRECTED 0x00000001
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#define ATA_SE_COMM_CORRECTED 0x00000002
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#define ATA_SE_DATA_ERR 0x00000100
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#define ATA_SE_COMM_ERR 0x00000200
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#define ATA_SE_PROT_ERR 0x00000400
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#define ATA_SE_HOST_ERR 0x00000800
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#define ATA_SE_PHY_CHANGED 0x00010000
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#define ATA_SE_PHY_IERROR 0x00020000
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#define ATA_SE_COMM_WAKE 0x00040000
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#define ATA_SE_DECODE_ERR 0x00080000
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#define ATA_SE_PARITY_ERR 0x00100000
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#define ATA_SE_CRC_ERR 0x00200000
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#define ATA_SE_HANDSHAKE_ERR 0x00400000
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#define ATA_SE_LINKSEQ_ERR 0x00800000
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#define ATA_SE_TRANSPORT_ERR 0x01000000
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#define ATA_SE_UNKNOWN_FIS 0x02000000
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#define ATA_SE_EXCHANGED 0x04000000
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#define ATA_SERROR 14
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#define ATA_SE_DATA_CORRECTED 0x00000001
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#define ATA_SE_COMM_CORRECTED 0x00000002
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#define ATA_SE_DATA_ERR 0x00000100
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#define ATA_SE_COMM_ERR 0x00000200
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#define ATA_SE_PROT_ERR 0x00000400
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#define ATA_SE_HOST_ERR 0x00000800
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#define ATA_SE_PHY_CHANGED 0x00010000
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#define ATA_SE_PHY_IERROR 0x00020000
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#define ATA_SE_COMM_WAKE 0x00040000
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#define ATA_SE_DECODE_ERR 0x00080000
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#define ATA_SE_PARITY_ERR 0x00100000
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#define ATA_SE_CRC_ERR 0x00200000
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#define ATA_SE_HANDSHAKE_ERR 0x00400000
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#define ATA_SE_LINKSEQ_ERR 0x00800000
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#define ATA_SE_TRANSPORT_ERR 0x01000000
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#define ATA_SE_UNKNOWN_FIS 0x02000000
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#define ATA_SE_EXCHANGED 0x04000000
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#define ATA_SCONTROL 15
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#define ATA_SC_DET_MASK 0x0000000f
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#define ATA_SC_DET_IDLE 0x00000000
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#define ATA_SC_DET_RESET 0x00000001
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#define ATA_SC_DET_DISABLE 0x00000004
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#define ATA_SCONTROL 15
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#define ATA_SC_DET_MASK 0x0000000f
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#define ATA_SC_DET_IDLE 0x00000000
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#define ATA_SC_DET_RESET 0x00000001
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#define ATA_SC_DET_DISABLE 0x00000004
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#define ATA_SC_SPD_MASK 0x000000f0
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#define ATA_SC_SPD_NO_SPEED 0x00000000
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#define ATA_SC_SPD_SPEED_GEN1 0x00000010
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#define ATA_SC_SPD_SPEED_GEN2 0x00000020
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#define ATA_SC_SPD_SPEED_GEN3 0x00000030
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#define ATA_SC_SPD_MASK 0x000000f0
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#define ATA_SC_SPD_NO_SPEED 0x00000000
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#define ATA_SC_SPD_SPEED_GEN1 0x00000010
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#define ATA_SC_SPD_SPEED_GEN2 0x00000020
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#define ATA_SC_SPD_SPEED_GEN3 0x00000030
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#define ATA_SC_IPM_MASK 0x00000f00
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#define ATA_SC_IPM_NONE 0x00000000
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
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#define ATA_SC_IPM_MASK 0x00000f00
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#define ATA_SC_IPM_NONE 0x00000000
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
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#define ATA_SACTIVE 16
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#define ATA_SACTIVE 16
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_SLOTS 32
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#define AHCI_MAX_IRQS 16
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_SLOTS 32
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#define AHCI_MAX_IRQS 16
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/* SATA AHCI v1.0 register defines */
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#define AHCI_CAP 0x00
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#define AHCI_CAP_NPMASK 0x0000001f
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#define AHCI_CAP_SXS 0x00000020
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#define AHCI_CAP_EMS 0x00000040
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#define AHCI_CAP_CCCS 0x00000080
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#define AHCI_CAP_NCS 0x00001F00
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#define AHCI_CAP_NCS_SHIFT 8
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#define AHCI_CAP_PSC 0x00002000
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#define AHCI_CAP_SSC 0x00004000
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#define AHCI_CAP_PMD 0x00008000
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#define AHCI_CAP_FBSS 0x00010000
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#define AHCI_CAP_SPM 0x00020000
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#define AHCI_CAP_SAM 0x00080000
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#define AHCI_CAP_ISS 0x00F00000
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#define AHCI_CAP_ISS_SHIFT 20
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#define AHCI_CAP_SCLO 0x01000000
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#define AHCI_CAP_SAL 0x02000000
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#define AHCI_CAP_SALP 0x04000000
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#define AHCI_CAP_SSS 0x08000000
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#define AHCI_CAP_SMPS 0x10000000
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#define AHCI_CAP_SSNTF 0x20000000
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#define AHCI_CAP_SNCQ 0x40000000
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#define AHCI_CAP_64BIT 0x80000000
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#define AHCI_CAP 0x00
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#define AHCI_CAP_NPMASK 0x0000001f
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#define AHCI_CAP_SXS 0x00000020
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#define AHCI_CAP_EMS 0x00000040
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#define AHCI_CAP_CCCS 0x00000080
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#define AHCI_CAP_NCS 0x00001F00
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#define AHCI_CAP_NCS_SHIFT 8
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#define AHCI_CAP_PSC 0x00002000
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#define AHCI_CAP_SSC 0x00004000
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#define AHCI_CAP_PMD 0x00008000
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#define AHCI_CAP_FBSS 0x00010000
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#define AHCI_CAP_SPM 0x00020000
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#define AHCI_CAP_SAM 0x00080000
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#define AHCI_CAP_ISS 0x00F00000
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#define AHCI_CAP_ISS_SHIFT 20
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#define AHCI_CAP_SCLO 0x01000000
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#define AHCI_CAP_SAL 0x02000000
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#define AHCI_CAP_SALP 0x04000000
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#define AHCI_CAP_SSS 0x08000000
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#define AHCI_CAP_SMPS 0x10000000
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#define AHCI_CAP_SSNTF 0x20000000
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#define AHCI_CAP_SNCQ 0x40000000
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#define AHCI_CAP_64BIT 0x80000000
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#define AHCI_GHC 0x04
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#define AHCI_GHC_AE 0x80000000
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#define AHCI_GHC_MRSM 0x00000004
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#define AHCI_GHC_IE 0x00000002
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#define AHCI_GHC_HR 0x00000001
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#define AHCI_GHC 0x04
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#define AHCI_GHC_AE 0x80000000
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#define AHCI_GHC_MRSM 0x00000004
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#define AHCI_GHC_IE 0x00000002
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#define AHCI_GHC_HR 0x00000001
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#define AHCI_IS 0x08
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#define AHCI_PI 0x0c
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#define AHCI_VS 0x10
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#define AHCI_IS 0x08
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#define AHCI_PI 0x0c
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#define AHCI_VS 0x10
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#define AHCI_CCCC 0x14
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#define AHCI_CCCC_TV_MASK 0xffff0000
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#define AHCI_CCCC_TV_SHIFT 16
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#define AHCI_CCCC_CC_MASK 0x0000ff00
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#define AHCI_CCCC_CC_SHIFT 8
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#define AHCI_CCCC_INT_MASK 0x000000f8
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#define AHCI_CCCC_INT_SHIFT 3
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#define AHCI_CCCC_EN 0x00000001
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#define AHCI_CCCP 0x18
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#define AHCI_CCCC 0x14
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#define AHCI_CCCC_TV_MASK 0xffff0000
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#define AHCI_CCCC_TV_SHIFT 16
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#define AHCI_CCCC_CC_MASK 0x0000ff00
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#define AHCI_CCCC_CC_SHIFT 8
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#define AHCI_CCCC_INT_MASK 0x000000f8
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#define AHCI_CCCC_INT_SHIFT 3
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#define AHCI_CCCC_EN 0x00000001
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#define AHCI_CCCP 0x18
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#define AHCI_EM_LOC 0x1C
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#define AHCI_EM_CTL 0x20
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#define AHCI_EM_MR 0x00000001
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#define AHCI_EM_TM 0x00000100
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#define AHCI_EM_RST 0x00000200
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#define AHCI_EM_LED 0x00010000
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#define AHCI_EM_SAFTE 0x00020000
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#define AHCI_EM_SES2 0x00040000
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#define AHCI_EM_SGPIO 0x00080000
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#define AHCI_EM_SMB 0x01000000
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#define AHCI_EM_XMT 0x02000000
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#define AHCI_EM_ALHD 0x04000000
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#define AHCI_EM_PM 0x08000000
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#define AHCI_EM_LOC 0x1C
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#define AHCI_EM_CTL 0x20
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#define AHCI_EM_MR 0x00000001
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#define AHCI_EM_TM 0x00000100
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#define AHCI_EM_RST 0x00000200
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#define AHCI_EM_LED 0x00010000
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#define AHCI_EM_SAFTE 0x00020000
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#define AHCI_EM_SES2 0x00040000
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#define AHCI_EM_SGPIO 0x00080000
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#define AHCI_EM_SMB 0x01000000
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#define AHCI_EM_XMT 0x02000000
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#define AHCI_EM_ALHD 0x04000000
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#define AHCI_EM_PM 0x08000000
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#define AHCI_CAP2 0x24
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#define AHCI_CAP2_BOH 0x00000001
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#define AHCI_CAP2_NVMP 0x00000002
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#define AHCI_CAP2_APST 0x00000004
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#define AHCI_CAP2_SDS 0x00000008
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#define AHCI_CAP2_SADM 0x00000010
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#define AHCI_CAP2_DESO 0x00000020
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#define AHCI_CAP2 0x24
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#define AHCI_CAP2_BOH 0x00000001
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#define AHCI_CAP2_NVMP 0x00000002
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#define AHCI_CAP2_APST 0x00000004
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#define AHCI_CAP2_SDS 0x00000008
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#define AHCI_CAP2_SADM 0x00000010
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#define AHCI_CAP2_DESO 0x00000020
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#define AHCI_OFFSET 0x100
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#define AHCI_STEP 0x80
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#define AHCI_OFFSET 0x100
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#define AHCI_STEP 0x80
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#define AHCI_P_CLB 0x00
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#define AHCI_P_CLBU 0x04
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#define AHCI_P_FB 0x08
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#define AHCI_P_FBU 0x0c
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#define AHCI_P_IS 0x10
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#define AHCI_P_IE 0x14
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#define AHCI_P_IX_DHR 0x00000001
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#define AHCI_P_IX_PS 0x00000002
|
||||
#define AHCI_P_IX_DS 0x00000004
|
||||
#define AHCI_P_IX_SDB 0x00000008
|
||||
#define AHCI_P_IX_UF 0x00000010
|
||||
#define AHCI_P_IX_DP 0x00000020
|
||||
#define AHCI_P_IX_PC 0x00000040
|
||||
#define AHCI_P_IX_MP 0x00000080
|
||||
#define AHCI_P_CLB 0x00
|
||||
#define AHCI_P_CLBU 0x04
|
||||
#define AHCI_P_FB 0x08
|
||||
#define AHCI_P_FBU 0x0c
|
||||
#define AHCI_P_IS 0x10
|
||||
#define AHCI_P_IE 0x14
|
||||
#define AHCI_P_IX_DHR 0x00000001
|
||||
#define AHCI_P_IX_PS 0x00000002
|
||||
#define AHCI_P_IX_DS 0x00000004
|
||||
#define AHCI_P_IX_SDB 0x00000008
|
||||
#define AHCI_P_IX_UF 0x00000010
|
||||
#define AHCI_P_IX_DP 0x00000020
|
||||
#define AHCI_P_IX_PC 0x00000040
|
||||
#define AHCI_P_IX_MP 0x00000080
|
||||
|
||||
#define AHCI_P_IX_PRC 0x00400000
|
||||
#define AHCI_P_IX_IPM 0x00800000
|
||||
#define AHCI_P_IX_OF 0x01000000
|
||||
#define AHCI_P_IX_INF 0x04000000
|
||||
#define AHCI_P_IX_IF 0x08000000
|
||||
#define AHCI_P_IX_HBD 0x10000000
|
||||
#define AHCI_P_IX_HBF 0x20000000
|
||||
#define AHCI_P_IX_TFE 0x40000000
|
||||
#define AHCI_P_IX_CPD 0x80000000
|
||||
#define AHCI_P_IX_PRC 0x00400000
|
||||
#define AHCI_P_IX_IPM 0x00800000
|
||||
#define AHCI_P_IX_OF 0x01000000
|
||||
#define AHCI_P_IX_INF 0x04000000
|
||||
#define AHCI_P_IX_IF 0x08000000
|
||||
#define AHCI_P_IX_HBD 0x10000000
|
||||
#define AHCI_P_IX_HBF 0x20000000
|
||||
#define AHCI_P_IX_TFE 0x40000000
|
||||
#define AHCI_P_IX_CPD 0x80000000
|
||||
|
||||
#define AHCI_P_CMD 0x18
|
||||
#define AHCI_P_CMD_ST 0x00000001
|
||||
#define AHCI_P_CMD_SUD 0x00000002
|
||||
#define AHCI_P_CMD_POD 0x00000004
|
||||
#define AHCI_P_CMD_CLO 0x00000008
|
||||
#define AHCI_P_CMD_FRE 0x00000010
|
||||
#define AHCI_P_CMD_CCS_MASK 0x00001f00
|
||||
#define AHCI_P_CMD_CCS_SHIFT 8
|
||||
#define AHCI_P_CMD_ISS 0x00002000
|
||||
#define AHCI_P_CMD_FR 0x00004000
|
||||
#define AHCI_P_CMD_CR 0x00008000
|
||||
#define AHCI_P_CMD_CPS 0x00010000
|
||||
#define AHCI_P_CMD_PMA 0x00020000
|
||||
#define AHCI_P_CMD_HPCP 0x00040000
|
||||
#define AHCI_P_CMD_MPSP 0x00080000
|
||||
#define AHCI_P_CMD_CPD 0x00100000
|
||||
#define AHCI_P_CMD_ESP 0x00200000
|
||||
#define AHCI_P_CMD_FBSCP 0x00400000
|
||||
#define AHCI_P_CMD_APSTE 0x00800000
|
||||
#define AHCI_P_CMD_ATAPI 0x01000000
|
||||
#define AHCI_P_CMD_DLAE 0x02000000
|
||||
#define AHCI_P_CMD_ALPE 0x04000000
|
||||
#define AHCI_P_CMD_ASP 0x08000000
|
||||
#define AHCI_P_CMD_ICC_MASK 0xf0000000
|
||||
#define AHCI_P_CMD_NOOP 0x00000000
|
||||
#define AHCI_P_CMD_ACTIVE 0x10000000
|
||||
#define AHCI_P_CMD_PARTIAL 0x20000000
|
||||
#define AHCI_P_CMD_SLUMBER 0x60000000
|
||||
#define AHCI_P_CMD_DEVSLEEP 0x80000000
|
||||
#define AHCI_P_CMD 0x18
|
||||
#define AHCI_P_CMD_ST 0x00000001
|
||||
#define AHCI_P_CMD_SUD 0x00000002
|
||||
#define AHCI_P_CMD_POD 0x00000004
|
||||
#define AHCI_P_CMD_CLO 0x00000008
|
||||
#define AHCI_P_CMD_FRE 0x00000010
|
||||
#define AHCI_P_CMD_CCS_MASK 0x00001f00
|
||||
#define AHCI_P_CMD_CCS_SHIFT 8
|
||||
#define AHCI_P_CMD_ISS 0x00002000
|
||||
#define AHCI_P_CMD_FR 0x00004000
|
||||
#define AHCI_P_CMD_CR 0x00008000
|
||||
#define AHCI_P_CMD_CPS 0x00010000
|
||||
#define AHCI_P_CMD_PMA 0x00020000
|
||||
#define AHCI_P_CMD_HPCP 0x00040000
|
||||
#define AHCI_P_CMD_MPSP 0x00080000
|
||||
#define AHCI_P_CMD_CPD 0x00100000
|
||||
#define AHCI_P_CMD_ESP 0x00200000
|
||||
#define AHCI_P_CMD_FBSCP 0x00400000
|
||||
#define AHCI_P_CMD_APSTE 0x00800000
|
||||
#define AHCI_P_CMD_ATAPI 0x01000000
|
||||
#define AHCI_P_CMD_DLAE 0x02000000
|
||||
#define AHCI_P_CMD_ALPE 0x04000000
|
||||
#define AHCI_P_CMD_ASP 0x08000000
|
||||
#define AHCI_P_CMD_ICC_MASK 0xf0000000
|
||||
#define AHCI_P_CMD_NOOP 0x00000000
|
||||
#define AHCI_P_CMD_ACTIVE 0x10000000
|
||||
#define AHCI_P_CMD_PARTIAL 0x20000000
|
||||
#define AHCI_P_CMD_SLUMBER 0x60000000
|
||||
#define AHCI_P_CMD_DEVSLEEP 0x80000000
|
||||
|
||||
#define AHCI_P_TFD 0x20
|
||||
#define AHCI_P_SIG 0x24
|
||||
#define AHCI_P_SSTS 0x28
|
||||
#define AHCI_P_SCTL 0x2c
|
||||
#define AHCI_P_SERR 0x30
|
||||
#define AHCI_P_SACT 0x34
|
||||
#define AHCI_P_CI 0x38
|
||||
#define AHCI_P_SNTF 0x3C
|
||||
#define AHCI_P_FBS 0x40
|
||||
#define AHCI_P_FBS_EN 0x00000001
|
||||
#define AHCI_P_FBS_DEC 0x00000002
|
||||
#define AHCI_P_FBS_SDE 0x00000004
|
||||
#define AHCI_P_FBS_DEV 0x00000f00
|
||||
#define AHCI_P_FBS_DEV_SHIFT 8
|
||||
#define AHCI_P_FBS_ADO 0x0000f000
|
||||
#define AHCI_P_FBS_ADO_SHIFT 12
|
||||
#define AHCI_P_FBS_DWE 0x000f0000
|
||||
#define AHCI_P_FBS_DWE_SHIFT 16
|
||||
#define AHCI_P_DEVSLP 0x44
|
||||
#define AHCI_P_DEVSLP_ADSE 0x00000001
|
||||
#define AHCI_P_DEVSLP_DSP 0x00000002
|
||||
#define AHCI_P_DEVSLP_DETO 0x000003fc
|
||||
#define AHCI_P_DEVSLP_DETO_SHIFT 2
|
||||
#define AHCI_P_DEVSLP_MDAT 0x00007c00
|
||||
#define AHCI_P_DEVSLP_MDAT_SHIFT 10
|
||||
#define AHCI_P_DEVSLP_DITO 0x01ff8000
|
||||
#define AHCI_P_DEVSLP_DITO_SHIFT 15
|
||||
#define AHCI_P_DEVSLP_DM 0x0e000000
|
||||
#define AHCI_P_DEVSLP_DM_SHIFT 25
|
||||
#define AHCI_P_TFD 0x20
|
||||
#define AHCI_P_SIG 0x24
|
||||
#define AHCI_P_SSTS 0x28
|
||||
#define AHCI_P_SCTL 0x2c
|
||||
#define AHCI_P_SERR 0x30
|
||||
#define AHCI_P_SACT 0x34
|
||||
#define AHCI_P_CI 0x38
|
||||
#define AHCI_P_SNTF 0x3C
|
||||
#define AHCI_P_FBS 0x40
|
||||
#define AHCI_P_FBS_EN 0x00000001
|
||||
#define AHCI_P_FBS_DEC 0x00000002
|
||||
#define AHCI_P_FBS_SDE 0x00000004
|
||||
#define AHCI_P_FBS_DEV 0x00000f00
|
||||
#define AHCI_P_FBS_DEV_SHIFT 8
|
||||
#define AHCI_P_FBS_ADO 0x0000f000
|
||||
#define AHCI_P_FBS_ADO_SHIFT 12
|
||||
#define AHCI_P_FBS_DWE 0x000f0000
|
||||
#define AHCI_P_FBS_DWE_SHIFT 16
|
||||
#define AHCI_P_DEVSLP 0x44
|
||||
#define AHCI_P_DEVSLP_ADSE 0x00000001
|
||||
#define AHCI_P_DEVSLP_DSP 0x00000002
|
||||
#define AHCI_P_DEVSLP_DETO 0x000003fc
|
||||
#define AHCI_P_DEVSLP_DETO_SHIFT 2
|
||||
#define AHCI_P_DEVSLP_MDAT 0x00007c00
|
||||
#define AHCI_P_DEVSLP_MDAT_SHIFT 10
|
||||
#define AHCI_P_DEVSLP_DITO 0x01ff8000
|
||||
#define AHCI_P_DEVSLP_DITO_SHIFT 15
|
||||
#define AHCI_P_DEVSLP_DM 0x0e000000
|
||||
#define AHCI_P_DEVSLP_DM_SHIFT 25
|
||||
|
||||
/* Just to be sure, if building as module. */
|
||||
#if MAXPHYS < 512 * 1024
|
||||
#undef MAXPHYS
|
||||
#define MAXPHYS 512 * 1024
|
||||
#define MAXPHYS 512 * 1024
|
||||
#endif
|
||||
/* Pessimistic prognosis on number of required S/G entries */
|
||||
#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
|
||||
#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
|
||||
/* Command list. 32 commands. First, 1Kbyte aligned. */
|
||||
#define AHCI_CL_OFFSET 0
|
||||
#define AHCI_CL_SIZE 32
|
||||
#define AHCI_CL_OFFSET 0
|
||||
#define AHCI_CL_SIZE 32
|
||||
/* Command tables. Up to 32 commands, Each, 128byte aligned. */
|
||||
#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
|
||||
#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
|
||||
#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
|
||||
#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
|
||||
/* Total main work area. */
|
||||
#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
|
||||
#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
|
||||
|
||||
#endif /* _AHCI_H_ */
|
||||
|
||||
@ -118,14 +118,14 @@ static void vm_loop(struct vmctx *ctx, int vcpu, uint64_t rip);
|
||||
static struct vm_exit vmexit[VM_MAXCPU];
|
||||
|
||||
struct bhyvestats {
|
||||
uint64_t vmexit_bogus;
|
||||
uint64_t vmexit_bogus;
|
||||
uint64_t vmexit_reqidle;
|
||||
uint64_t vmexit_hlt;
|
||||
uint64_t vmexit_pause;
|
||||
uint64_t vmexit_mtrap;
|
||||
uint64_t vmexit_inst_emul;
|
||||
uint64_t cpu_switch_rotate;
|
||||
uint64_t cpu_switch_direct;
|
||||
uint64_t vmexit_hlt;
|
||||
uint64_t vmexit_pause;
|
||||
uint64_t vmexit_mtrap;
|
||||
uint64_t vmexit_inst_emul;
|
||||
uint64_t cpu_switch_rotate;
|
||||
uint64_t cpu_switch_direct;
|
||||
} stats;
|
||||
|
||||
struct mt_vmm_info {
|
||||
@ -413,7 +413,7 @@ vmexit_handle_notify(struct vmctx *ctx, struct vm_exit *vme, int *pvcpu,
|
||||
* put guest-driven debug here
|
||||
*/
|
||||
#endif
|
||||
return (VMEXIT_CONTINUE);
|
||||
return (VMEXIT_CONTINUE);
|
||||
}
|
||||
|
||||
static int
|
||||
|
||||
@ -101,8 +101,8 @@ struct blockif_ctxt {
|
||||
int bc_psectoff;
|
||||
int bc_closing;
|
||||
pthread_t bc_btid[BLOCKIF_NUMTHR];
|
||||
pthread_mutex_t bc_mtx;
|
||||
pthread_cond_t bc_cond;
|
||||
pthread_mutex_t bc_mtx;
|
||||
pthread_cond_t bc_cond;
|
||||
|
||||
/* Request elements and free/pending/busy queues */
|
||||
TAILQ_HEAD(, blockif_elem) bc_freeq;
|
||||
|
||||
@ -35,6 +35,6 @@
|
||||
|
||||
struct vmctx;
|
||||
|
||||
int bootrom_init(struct vmctx *ctx, const char *romfile);
|
||||
int bootrom_init(struct vmctx *ctx, const char *romfile);
|
||||
|
||||
#endif
|
||||
|
||||
@ -37,19 +37,19 @@ typedef void (*fb_render_func_t)(struct bhyvegc *gc, void *arg);
|
||||
typedef void (*kbd_event_func_t)(int down, uint32_t keysym, void *arg);
|
||||
typedef void (*ptr_event_func_t)(uint8_t mask, int x, int y, void *arg);
|
||||
|
||||
void console_init(int w, int h, void *fbaddr);
|
||||
void console_init(int w, int h, void *fbaddr);
|
||||
|
||||
void console_set_fbaddr(void *fbaddr);
|
||||
void console_set_fbaddr(void *fbaddr);
|
||||
|
||||
struct bhyvegc_image *console_get_image(void);
|
||||
|
||||
void console_fb_register(fb_render_func_t render_cb, void *arg);
|
||||
void console_refresh(void);
|
||||
void console_fb_register(fb_render_func_t render_cb, void *arg);
|
||||
void console_refresh(void);
|
||||
|
||||
void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri);
|
||||
void console_key_event(int down, uint32_t keysym);
|
||||
void console_kbd_register(kbd_event_func_t event_cb, void *arg, int pri);
|
||||
void console_key_event(int down, uint32_t keysym);
|
||||
|
||||
void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri);
|
||||
void console_ptr_event(uint8_t button, int x, int y);
|
||||
void console_ptr_register(ptr_event_func_t event_cb, void *arg, int pri);
|
||||
void console_ptr_event(uint8_t button, int x, int y);
|
||||
|
||||
#endif /* _CONSOLE_H_ */
|
||||
|
||||
@ -74,14 +74,14 @@ ttyopen(void)
|
||||
static bool
|
||||
tty_char_available(void)
|
||||
{
|
||||
fd_set rfds;
|
||||
struct timeval tv;
|
||||
fd_set rfds;
|
||||
struct timeval tv;
|
||||
|
||||
FD_ZERO(&rfds);
|
||||
FD_SET(STDIN_FILENO, &rfds);
|
||||
tv.tv_sec = 0;
|
||||
tv.tv_usec = 0;
|
||||
if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) {
|
||||
FD_ZERO(&rfds);
|
||||
FD_SET(STDIN_FILENO, &rfds);
|
||||
tv.tv_sec = 0;
|
||||
tv.tv_usec = 0;
|
||||
if (select(STDIN_FILENO + 1, &rfds, NULL, NULL, &tv) > 0) {
|
||||
return (true);
|
||||
} else {
|
||||
return (false);
|
||||
|
||||
@ -68,21 +68,21 @@ static int
|
||||
default_inout(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
||||
uint32_t *eax, void *arg)
|
||||
{
|
||||
if (in) {
|
||||
switch (bytes) {
|
||||
case 4:
|
||||
*eax = 0xffffffff;
|
||||
break;
|
||||
case 2:
|
||||
*eax = 0xffff;
|
||||
break;
|
||||
case 1:
|
||||
*eax = 0xff;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
if (in) {
|
||||
switch (bytes) {
|
||||
case 4:
|
||||
*eax = 0xffffffff;
|
||||
break;
|
||||
case 2:
|
||||
*eax = 0xffff;
|
||||
break;
|
||||
case 1:
|
||||
*eax = 0xff;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
|
||||
@ -55,7 +55,7 @@ struct mem_range {
|
||||
void init_mem(void);
|
||||
int emulate_mem(struct vmctx *, int vcpu, uint64_t paddr, struct vie *vie,
|
||||
struct vm_guest_paging *paging);
|
||||
|
||||
|
||||
int read_mem(struct vmctx *ctx, int vcpu, uint64_t gpa, uint64_t *rval,
|
||||
int size);
|
||||
int register_mem(struct mem_range *memp);
|
||||
|
||||
@ -71,7 +71,7 @@ static int mevent_timid = 43;
|
||||
static int mevent_pipefd[2];
|
||||
static pthread_mutex_t mevent_lmutex = PTHREAD_MUTEX_INITIALIZER;
|
||||
|
||||
struct mevent {
|
||||
struct mevent {
|
||||
void (*me_func)(int, enum ev_type, void *);
|
||||
#define me_msecs me_fd
|
||||
int me_fd;
|
||||
@ -81,7 +81,7 @@ struct mevent {
|
||||
int me_cq;
|
||||
int me_state;
|
||||
int me_closefd;
|
||||
LIST_ENTRY(mevent) me_list;
|
||||
LIST_ENTRY(mevent) me_list;
|
||||
};
|
||||
|
||||
static LIST_HEAD(listhead, mevent) global_head, change_head;
|
||||
|
||||
@ -199,25 +199,25 @@ acceptor(void *param)
|
||||
int s;
|
||||
static int first;
|
||||
|
||||
if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
|
||||
perror("socket");
|
||||
exit(1);
|
||||
}
|
||||
if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
|
||||
perror("socket");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
sin.sin_len = sizeof(sin);
|
||||
sin.sin_family = AF_INET;
|
||||
sin.sin_addr.s_addr = htonl(INADDR_ANY);
|
||||
sin.sin_port = htons(TEST_PORT);
|
||||
sin.sin_len = sizeof(sin);
|
||||
sin.sin_family = AF_INET;
|
||||
sin.sin_addr.s_addr = htonl(INADDR_ANY);
|
||||
sin.sin_port = htons(TEST_PORT);
|
||||
|
||||
if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) {
|
||||
perror("bind");
|
||||
exit(1);
|
||||
}
|
||||
if (bind(s, (struct sockaddr *)&sin, sizeof(sin)) < 0) {
|
||||
perror("bind");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (listen(s, 1) < 0) {
|
||||
perror("listen");
|
||||
exit(1);
|
||||
}
|
||||
if (listen(s, 1) < 0) {
|
||||
perror("listen");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
(void) mevent_add(s, EVF_READ, acceptor_callback, NULL);
|
||||
|
||||
|
||||
@ -344,8 +344,8 @@ struct e82545_softc {
|
||||
#define E82545_NVM_MODE_OPADDR 0x0
|
||||
#define E82545_NVM_MODE_DATAIN 0x1
|
||||
#define E82545_NVM_MODE_DATAOUT 0x2
|
||||
/* EEPROM data */
|
||||
uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
|
||||
/* EEPROM data */
|
||||
uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE];
|
||||
};
|
||||
|
||||
static void e82545_reset(struct e82545_softc *sc, int dev);
|
||||
@ -1472,7 +1472,7 @@ e82545_rx_disable(struct e82545_softc *sc)
|
||||
static void
|
||||
e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
|
||||
{
|
||||
struct eth_uni *eu;
|
||||
struct eth_uni *eu;
|
||||
int idx;
|
||||
|
||||
idx = reg >> 1;
|
||||
@ -1498,7 +1498,7 @@ e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval)
|
||||
static uint32_t
|
||||
e82545_read_ra(struct e82545_softc *sc, int reg)
|
||||
{
|
||||
struct eth_uni *eu;
|
||||
struct eth_uni *eu;
|
||||
uint32_t retval;
|
||||
int idx;
|
||||
|
||||
@ -1742,12 +1742,12 @@ e82545_read_register(struct e82545_softc *sc, uint32_t offset)
|
||||
{
|
||||
uint32_t retval;
|
||||
int ridx;
|
||||
|
||||
|
||||
if (offset & 0x3) {
|
||||
DPRINTF("Unaligned register read offset:0x%x\r\n", offset);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
DPRINTF("Register read: 0x%x\r\n", offset);
|
||||
|
||||
switch (offset) {
|
||||
|
||||
@ -863,7 +863,7 @@ msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
|
||||
{
|
||||
uint16_t msgctrl, rwmask;
|
||||
int off;
|
||||
|
||||
|
||||
off = offset - capoff;
|
||||
/* Message Control Register */
|
||||
if (off == 2 && bytes == 2) {
|
||||
@ -876,8 +876,8 @@ msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
|
||||
pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
|
||||
pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
|
||||
pci_lintr_update(pi);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
CFGWRITE(pi, offset, val, bytes);
|
||||
}
|
||||
|
||||
@ -1336,11 +1336,11 @@ pci_bus_write_dsdt(int bus)
|
||||
dsdt_line("Name (PPRT, Package ()");
|
||||
dsdt_line("{");
|
||||
pci_walk_lintr(bus, pci_pirq_prt_entry, NULL);
|
||||
dsdt_line("})");
|
||||
dsdt_line("})");
|
||||
dsdt_line("Name (APRT, Package ()");
|
||||
dsdt_line("{");
|
||||
pci_walk_lintr(bus, pci_apic_prt_entry, NULL);
|
||||
dsdt_line("})");
|
||||
dsdt_line("})");
|
||||
dsdt_line("Method (_PRT, 0, NotSerialized)");
|
||||
dsdt_line("{");
|
||||
dsdt_line(" If (PICM)");
|
||||
@ -1726,7 +1726,7 @@ pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
|
||||
* interrupt.
|
||||
*/
|
||||
pci_lintr_update(pi);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
|
||||
|
||||
@ -726,24 +726,24 @@ pci_vtnet_ping_ctlq(void *vsc, struct vqueue_info *vq)
|
||||
static int
|
||||
pci_vtnet_parsemac(char *mac_str, uint8_t *mac_addr)
|
||||
{
|
||||
struct ether_addr *ea;
|
||||
char *tmpstr;
|
||||
char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
|
||||
struct ether_addr *ea;
|
||||
char *tmpstr;
|
||||
char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
tmpstr = strsep(&mac_str,"=");
|
||||
|
||||
if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) {
|
||||
ea = ether_aton(mac_str);
|
||||
tmpstr = strsep(&mac_str,"=");
|
||||
|
||||
if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) ||
|
||||
memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) {
|
||||
if ((mac_str != NULL) && (!strcmp(tmpstr,"mac"))) {
|
||||
ea = ether_aton(mac_str);
|
||||
|
||||
if (ea == NULL || ETHER_IS_MULTICAST(ea->octet) ||
|
||||
memcmp(ea->octet, zero_addr, ETHER_ADDR_LEN) == 0) {
|
||||
fprintf(stderr, "Invalid MAC %s\n", mac_str);
|
||||
return (EINVAL);
|
||||
} else
|
||||
memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN);
|
||||
}
|
||||
return (EINVAL);
|
||||
} else
|
||||
memcpy(mac_addr, ea->octet, ETHER_ADDR_LEN);
|
||||
}
|
||||
|
||||
return (0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -932,7 +932,7 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
pthread_create(&sc->tx_tid, NULL, pci_vtnet_tx_thread, (void *)sc);
|
||||
snprintf(tname, sizeof(tname), "vtnet-%d:%d tx", pi->pi_slot,
|
||||
pi->pi_func);
|
||||
pthread_set_name_np(sc->tx_tid, tname);
|
||||
pthread_set_name_np(sc->tx_tid, tname);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -2212,12 +2212,12 @@ pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
|
||||
sc = pi->pi_arg;
|
||||
|
||||
assert(baridx == 0);
|
||||
assert(baridx == 0);
|
||||
|
||||
|
||||
pthread_mutex_lock(&sc->mtx);
|
||||
pthread_mutex_lock(&sc->mtx);
|
||||
if (offset < XHCI_CAPLEN) /* read only registers */
|
||||
WPRINTF(("pci_xhci: write RO-CAPs offset %ld\r\n", offset));
|
||||
WPRINTF(("pci_xhci: write RO-CAPs offset %ld\r\n", offset));
|
||||
else if (offset < sc->dboff)
|
||||
pci_xhci_hostop_write(sc, offset, value);
|
||||
else if (offset < sc->rtsoff)
|
||||
@ -2225,9 +2225,9 @@ pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
else if (offset < sc->regsend)
|
||||
pci_xhci_rtsregs_write(sc, offset, value);
|
||||
else
|
||||
WPRINTF(("pci_xhci: write invalid offset %ld\r\n", offset));
|
||||
WPRINTF(("pci_xhci: write invalid offset %ld\r\n", offset));
|
||||
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
}
|
||||
|
||||
static uint64_t
|
||||
@ -2435,9 +2435,9 @@ pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
||||
|
||||
sc = pi->pi_arg;
|
||||
|
||||
assert(baridx == 0);
|
||||
assert(baridx == 0);
|
||||
|
||||
pthread_mutex_lock(&sc->mtx);
|
||||
pthread_mutex_lock(&sc->mtx);
|
||||
if (offset < XHCI_CAPLEN)
|
||||
value = pci_xhci_hostcap_read(sc, offset);
|
||||
else if (offset < sc->dboff)
|
||||
@ -2450,10 +2450,10 @@ pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
|
||||
value = pci_xhci_xecp_read(sc, offset);
|
||||
else {
|
||||
value = 0;
|
||||
WPRINTF(("pci_xhci: read invalid offset %ld\r\n", offset));
|
||||
WPRINTF(("pci_xhci: read invalid offset %ld\r\n", offset));
|
||||
}
|
||||
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
pthread_mutex_unlock(&sc->mtx);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
|
||||
@ -74,11 +74,11 @@ static int rfb_debug = 0;
|
||||
#define AUTH_LENGTH 16
|
||||
#define PASSWD_LENGTH 8
|
||||
|
||||
#define SECURITY_TYPE_NONE 1
|
||||
#define SECURITY_TYPE_VNC_AUTH 2
|
||||
#define SECURITY_TYPE_NONE 1
|
||||
#define SECURITY_TYPE_VNC_AUTH 2
|
||||
|
||||
#define AUTH_FAILED_UNAUTH 1
|
||||
#define AUTH_FAILED_ERROR 2
|
||||
#define AUTH_FAILED_UNAUTH 1
|
||||
#define AUTH_FAILED_ERROR 2
|
||||
|
||||
struct rfb_softc {
|
||||
int sfd;
|
||||
@ -140,12 +140,12 @@ struct rfb_pixfmt_msg {
|
||||
#define RFB_ENCODING_ZLIB 6
|
||||
#define RFB_ENCODING_RESIZE -223
|
||||
|
||||
#define RFB_MAX_WIDTH 2000
|
||||
#define RFB_MAX_HEIGHT 1200
|
||||
#define RFB_MAX_WIDTH 2000
|
||||
#define RFB_MAX_HEIGHT 1200
|
||||
#define RFB_ZLIB_BUFSZ RFB_MAX_WIDTH*RFB_MAX_HEIGHT*4
|
||||
|
||||
/* percentage changes to screen before sending the entire screen */
|
||||
#define RFB_SEND_ALL_THRESH 25
|
||||
#define RFB_SEND_ALL_THRESH 25
|
||||
|
||||
struct rfb_enc_msg {
|
||||
uint8_t type;
|
||||
@ -306,7 +306,7 @@ rfb_send_rect(struct rfb_softc *rc, int cfd, struct bhyvegc_image *gc,
|
||||
int x, int y, int w, int h)
|
||||
{
|
||||
struct rfb_srvr_updt_msg supdt_msg;
|
||||
struct rfb_srvr_rect_hdr srect_hdr;
|
||||
struct rfb_srvr_rect_hdr srect_hdr;
|
||||
unsigned long zlen;
|
||||
ssize_t nwrite, total;
|
||||
int err;
|
||||
@ -466,9 +466,9 @@ rfb_send_all(struct rfb_softc *rc, int cfd, struct bhyvegc_image *gc)
|
||||
return (nwrite);
|
||||
}
|
||||
|
||||
#define PIX_PER_CELL 32
|
||||
#define PIX_PER_CELL 32
|
||||
#define PIXCELL_SHIFT 5
|
||||
#define PIXCELL_MASK 0x1F
|
||||
#define PIXCELL_MASK 0x1F
|
||||
|
||||
static int
|
||||
rfb_send_screen(struct rfb_softc *rc, int cfd, int all)
|
||||
@ -714,7 +714,7 @@ rfb_wr_thr(void *arg)
|
||||
tv.tv_usec = 10000;
|
||||
|
||||
err = select(cfd+1, &rfds, NULL, NULL, &tv);
|
||||
if (err < 0)
|
||||
if (err < 0)
|
||||
return (NULL);
|
||||
|
||||
/* Determine if its time to push screen; ~24hz */
|
||||
|
||||
@ -51,7 +51,7 @@ __FBSDID("$FreeBSD$");
|
||||
#define RTC_HMEM_SB 0x5c
|
||||
#define RTC_HMEM_MSB 0x5d
|
||||
|
||||
#define m_64KB (64*1024)
|
||||
#define m_64KB (64*1024)
|
||||
#define m_16MB (16*1024*1024)
|
||||
#define m_4GB (4ULL*1024*1024*1024)
|
||||
|
||||
|
||||
@ -84,5 +84,3 @@ stream_write(int fd, const void *buf, ssize_t nbytes)
|
||||
}
|
||||
return (len);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -56,9 +56,9 @@ __FBSDID("$FreeBSD$");
|
||||
#include "uart_emul.h"
|
||||
|
||||
#define COM1_BASE 0x3F8
|
||||
#define COM1_IRQ 4
|
||||
#define COM1_IRQ 4
|
||||
#define COM2_BASE 0x2F8
|
||||
#define COM2_IRQ 3
|
||||
#define COM2_IRQ 3
|
||||
|
||||
#define DEFAULT_RCLK 1843200
|
||||
#define DEFAULT_BAUD 9600
|
||||
@ -71,7 +71,7 @@ __FBSDID("$FreeBSD$");
|
||||
#define MSR_DELTA_MASK 0x0f
|
||||
|
||||
#ifndef REG_SCR
|
||||
#define REG_SCR com_scr
|
||||
#define REG_SCR com_scr
|
||||
#endif
|
||||
|
||||
#define FIFOSZ 16
|
||||
|
||||
@ -222,16 +222,16 @@ struct umouse_bos_desc umouse_bosd = {
|
||||
HSETW(.wTotalLength, sizeof(umouse_bosd)),
|
||||
.bNumDeviceCaps = 1,
|
||||
},
|
||||
.usbssd = {
|
||||
.bLength = sizeof(umouse_bosd.usbssd),
|
||||
.bDescriptorType = UDESC_DEVICE_CAPABILITY,
|
||||
.bDevCapabilityType = 3,
|
||||
.bmAttributes = 0,
|
||||
HSETW(.wSpeedsSupported, 0x08),
|
||||
.bFunctionalitySupport = 3,
|
||||
.bU1DevExitLat = 0xa, /* dummy - not used */
|
||||
.wU2DevExitLat = { 0x20, 0x00 },
|
||||
}
|
||||
.usbssd = {
|
||||
.bLength = sizeof(umouse_bosd.usbssd),
|
||||
.bDescriptorType = UDESC_DEVICE_CAPABILITY,
|
||||
.bDevCapabilityType = 3,
|
||||
.bmAttributes = 0,
|
||||
HSETW(.wSpeedsSupported, 0x08),
|
||||
.bFunctionalitySupport = 3,
|
||||
.bU1DevExitLat = 0xa, /* dummy - not used */
|
||||
.wU2DevExitLat = { 0x20, 0x00 },
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -40,8 +40,8 @@
|
||||
#define GEN_MISC_OUTPUT_PORT 0x3cc
|
||||
#define GEN_INPUT_STS1_MONO_PORT 0x3ba
|
||||
#define GEN_INPUT_STS1_COLOR_PORT 0x3da
|
||||
#define GEN_IS1_VR 0x08 /* Vertical retrace */
|
||||
#define GEN_IS1_DE 0x01 /* Display enable not */
|
||||
#define GEN_IS1_VR 0x08 /* Vertical retrace */
|
||||
#define GEN_IS1_DE 0x01 /* Display enable not */
|
||||
|
||||
/* Attribute controller registers. */
|
||||
#define ATC_IDX_PORT 0x3c0
|
||||
@ -51,14 +51,14 @@
|
||||
#define ATC_PALETTE0 0
|
||||
#define ATC_PALETTE15 15
|
||||
#define ATC_MODE_CONTROL 16
|
||||
#define ATC_MC_IPS 0x80 /* Internal palette size */
|
||||
#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
|
||||
#define ATC_MC_IPS 0x80 /* Internal palette size */
|
||||
#define ATC_MC_GA 0x01 /* Graphics/alphanumeric */
|
||||
#define ATC_OVERSCAN_COLOR 17
|
||||
#define ATC_COLOR_PLANE_ENABLE 18
|
||||
#define ATC_HORIZ_PIXEL_PANNING 19
|
||||
#define ATC_COLOR_SELECT 20
|
||||
#define ATC_CS_C67 0x0c /* Color select bits 6+7 */
|
||||
#define ATC_CS_C45 0x03 /* Color select bits 4+5 */
|
||||
#define ATC_CS_C67 0x0c /* Color select bits 6+7 */
|
||||
#define ATC_CS_C45 0x03 /* Color select bits 4+5 */
|
||||
|
||||
/* Sequencer registers. */
|
||||
#define SEQ_IDX_PORT 0x3c4
|
||||
@ -68,22 +68,22 @@
|
||||
#define SEQ_RESET_ASYNC 0x1
|
||||
#define SEQ_RESET_SYNC 0x2
|
||||
#define SEQ_CLOCKING_MODE 1
|
||||
#define SEQ_CM_SO 0x20 /* Screen off */
|
||||
#define SEQ_CM_89 0x01 /* 8/9 dot clock */
|
||||
#define SEQ_CM_SO 0x20 /* Screen off */
|
||||
#define SEQ_CM_89 0x01 /* 8/9 dot clock */
|
||||
#define SEQ_MAP_MASK 2
|
||||
#define SEQ_CHAR_MAP_SELECT 3
|
||||
#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
|
||||
#define SEQ_CMS_SAH_SHIFT 5
|
||||
#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
|
||||
#define SEQ_CMS_SA_SHIFT 2
|
||||
#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
|
||||
#define SEQ_CMS_SBH_SHIFT 4
|
||||
#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
|
||||
#define SEQ_CMS_SB_SHIFT 0
|
||||
#define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */
|
||||
#define SEQ_CMS_SAH_SHIFT 5
|
||||
#define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */
|
||||
#define SEQ_CMS_SA_SHIFT 2
|
||||
#define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */
|
||||
#define SEQ_CMS_SBH_SHIFT 4
|
||||
#define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */
|
||||
#define SEQ_CMS_SB_SHIFT 0
|
||||
#define SEQ_MEMORY_MODE 4
|
||||
#define SEQ_MM_C4 0x08 /* Chain 4 */
|
||||
#define SEQ_MM_OE 0x04 /* Odd/even */
|
||||
#define SEQ_MM_EM 0x02 /* Extended memory */
|
||||
#define SEQ_MM_C4 0x08 /* Chain 4 */
|
||||
#define SEQ_MM_OE 0x04 /* Odd/even */
|
||||
#define SEQ_MM_EM 0x02 /* Extended memory */
|
||||
|
||||
/* Graphics controller registers. */
|
||||
#define GC_IDX_PORT 0x3ce
|
||||
@ -95,13 +95,13 @@
|
||||
#define GC_DATA_ROTATE 3
|
||||
#define GC_READ_MAP_SELECT 4
|
||||
#define GC_MODE 5
|
||||
#define GC_MODE_OE 0x10 /* Odd/even */
|
||||
#define GC_MODE_C4 0x04 /* Chain 4 */
|
||||
#define GC_MODE_OE 0x10 /* Odd/even */
|
||||
#define GC_MODE_C4 0x04 /* Chain 4 */
|
||||
|
||||
#define GC_MISCELLANEOUS 6
|
||||
#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
|
||||
#define GC_MISC_MM 0x0c /* memory map */
|
||||
#define GC_MISC_MM_SHIFT 2
|
||||
#define GC_MISC_GM 0x01 /* Graphics/alphanumeric */
|
||||
#define GC_MISC_MM 0x0c /* memory map */
|
||||
#define GC_MISC_MM_SHIFT 2
|
||||
#define GC_COLOR_DONT_CARE 7
|
||||
#define GC_BIT_MASK 8
|
||||
|
||||
@ -119,36 +119,36 @@
|
||||
#define CRTC_END_HORIZ_RETRACE 5
|
||||
#define CRTC_VERT_TOTAL 6
|
||||
#define CRTC_OVERFLOW 7
|
||||
#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
|
||||
#define CRTC_OF_VRS9_SHIFT 7
|
||||
#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
|
||||
#define CRTC_OF_VDE9_SHIFT 6
|
||||
#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
|
||||
#define CRTC_OF_VRS8_SHIFT 2
|
||||
#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
|
||||
#define CRTC_OF_VDE8_SHIFT 1
|
||||
#define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
|
||||
#define CRTC_OF_VRS9_SHIFT 7
|
||||
#define CRTC_OF_VDE9 0x40 /* VDE bit 9 */
|
||||
#define CRTC_OF_VDE9_SHIFT 6
|
||||
#define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
|
||||
#define CRTC_OF_VRS8_SHIFT 2
|
||||
#define CRTC_OF_VDE8 0x02 /* VDE bit 8 */
|
||||
#define CRTC_OF_VDE8_SHIFT 1
|
||||
#define CRTC_PRESET_ROW_SCAN 8
|
||||
#define CRTC_MAX_SCAN_LINE 9
|
||||
#define CRTC_MSL_MSL 0x1f
|
||||
#define CRTC_MSL_MSL 0x1f
|
||||
#define CRTC_CURSOR_START 10
|
||||
#define CRTC_CS_CO 0x20 /* Cursor off */
|
||||
#define CRTC_CS_CS 0x1f /* Cursor start */
|
||||
#define CRTC_CS_CO 0x20 /* Cursor off */
|
||||
#define CRTC_CS_CS 0x1f /* Cursor start */
|
||||
#define CRTC_CURSOR_END 11
|
||||
#define CRTC_CE_CE 0x1f /* Cursor end */
|
||||
#define CRTC_CE_CE 0x1f /* Cursor end */
|
||||
#define CRTC_START_ADDR_HIGH 12
|
||||
#define CRTC_START_ADDR_LOW 13
|
||||
#define CRTC_CURSOR_LOC_HIGH 14
|
||||
#define CRTC_CURSOR_LOC_LOW 15
|
||||
#define CRTC_VERT_RETRACE_START 16
|
||||
#define CRTC_VERT_RETRACE_END 17
|
||||
#define CRTC_VRE_MASK 0xf
|
||||
#define CRTC_VRE_MASK 0xf
|
||||
#define CRTC_VERT_DISP_END 18
|
||||
#define CRTC_OFFSET 19
|
||||
#define CRTC_UNDERLINE_LOC 20
|
||||
#define CRTC_START_VERT_BLANK 21
|
||||
#define CRTC_END_VERT_BLANK 22
|
||||
#define CRTC_MODE_CONTROL 23
|
||||
#define CRTC_MC_TE 0x80 /* Timing enable */
|
||||
#define CRTC_MC_TE 0x80 /* Timing enable */
|
||||
#define CRTC_LINE_COMPARE 24
|
||||
|
||||
/* DAC registers */
|
||||
|
||||
@ -51,7 +51,7 @@ __FBSDID("$FreeBSD$");
|
||||
* front of virtio-based device softc" constraint, let's use
|
||||
* this to convert.
|
||||
*/
|
||||
#define DEV_SOFTC(vs) ((void *)(vs))
|
||||
#define DEV_SOFTC(vs) ((void *)(vs))
|
||||
|
||||
/*
|
||||
* Link a virtio_softc to its constants, the device softc, and
|
||||
|
||||
@ -186,7 +186,7 @@ struct vring_used {
|
||||
/*
|
||||
* PFN register shift amount
|
||||
*/
|
||||
#define VRING_PFN 12
|
||||
#define VRING_PFN 12
|
||||
|
||||
/*
|
||||
* Virtio device types
|
||||
@ -224,19 +224,19 @@ struct vring_used {
|
||||
* If MSI-X is not enabled, those two registers disappear and
|
||||
* the remaining configuration registers start at offset 20.
|
||||
*/
|
||||
#define VTCFG_R_HOSTCAP 0
|
||||
#define VTCFG_R_GUESTCAP 4
|
||||
#define VTCFG_R_PFN 8
|
||||
#define VTCFG_R_QNUM 12
|
||||
#define VTCFG_R_QSEL 14
|
||||
#define VTCFG_R_QNOTIFY 16
|
||||
#define VTCFG_R_STATUS 18
|
||||
#define VTCFG_R_ISR 19
|
||||
#define VTCFG_R_CFGVEC 20
|
||||
#define VTCFG_R_QVEC 22
|
||||
#define VTCFG_R_CFG0 20 /* No MSI-X */
|
||||
#define VTCFG_R_CFG1 24 /* With MSI-X */
|
||||
#define VTCFG_R_MSIX 20
|
||||
#define VTCFG_R_HOSTCAP 0
|
||||
#define VTCFG_R_GUESTCAP 4
|
||||
#define VTCFG_R_PFN 8
|
||||
#define VTCFG_R_QNUM 12
|
||||
#define VTCFG_R_QSEL 14
|
||||
#define VTCFG_R_QNOTIFY 16
|
||||
#define VTCFG_R_STATUS 18
|
||||
#define VTCFG_R_ISR 19
|
||||
#define VTCFG_R_CFGVEC 20
|
||||
#define VTCFG_R_QVEC 22
|
||||
#define VTCFG_R_CFG0 20 /* No MSI-X */
|
||||
#define VTCFG_R_CFG1 24 /* With MSI-X */
|
||||
#define VTCFG_R_MSIX 20
|
||||
|
||||
/*
|
||||
* Bits in VTCFG_R_STATUS. Guests need not actually set any of these,
|
||||
@ -255,7 +255,7 @@ struct vring_used {
|
||||
#define VTCFG_ISR_QUEUES 0x01 /* re-scan queues */
|
||||
#define VTCFG_ISR_CONF_CHANGED 0x80 /* configuration changed */
|
||||
|
||||
#define VIRTIO_MSI_NO_VECTOR 0xFFFF
|
||||
#define VIRTIO_MSI_NO_VECTOR 0xFFFF
|
||||
|
||||
/*
|
||||
* Feature flags.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user