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dtrace instruction decoder: add 0x0f 0x1f NOP opcode support

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According to the AMD manual the whole range from 0x09 to 0x1f are NOPs.
Intel manual mentions only 0x1f.  Use only Intel one for now, it seems
to be the one actually generated by compilers.
Use gdb mnemonic for the operation: "nopw".

[1] AMD64 Architecture Programmer's Manual
    Volume 3: General-Purpose and System Instructions
[2] Software Optimization Guide for AMD Family 10h Processors
[3] Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
    Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z

Tested by:	Fabian Keil <freebsd-listen@fabiankeil.de> (earlier version)
MFC after:	3 days
This commit is contained in:
Andriy Gapon 2012-06-29 07:35:37 +00:00
parent c2353ed4c0
commit f724c6a137
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=237748
2 changed files with 2 additions and 2 deletions
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2
sys/cddl/dev/dtrace/amd64/dis_tables.c
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@ -815,7 +815,7 @@ const instable_t dis_op0F[16][16] = {
/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
/* [1C] */ INVALID, INVALID, INVALID, INVALID,
/* [1C] */ INVALID, INVALID, INVALID, TNS("nopw", M),
}, {
/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,

2
sys/cddl/dev/dtrace/i386/dis_tables.c
View File

@ -815,7 +815,7 @@ const instable_t dis_op0F[16][16] = {
/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
/* [1C] */ INVALID, INVALID, INVALID, INVALID,
/* [1C] */ INVALID, INVALID, INVALID, TNS("nopw", M),
}, {
/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,