- Include the T5 firmware with the driver.
- Update the T4 firmware to the latest. - Minor reorganization and updates to the version macros, etc. Obtained from: Chelsio MFC after: 1 day
This commit is contained in:
parent
8383a92e5b
commit
f72b68a1bf
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=252661
@ -1185,10 +1185,34 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.8.4.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.8.11.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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t5fw_cfg.c optional cxgbe \
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compile-with "${AWK} -f $S/tools/fw_stub.awk t5fw_cfg.fw:t5fw_cfg t5fw.fw:t5fw -mt5fw_cfg -c${.TARGET}" \
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no-implicit-rule before-depend local \
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clean "t5fw_cfg.c"
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t5fw_cfg.fwo optional cxgbe \
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dependency "t5fw_cfg.fw" \
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compile-with "${NORMAL_FWO}" \
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no-implicit-rule \
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clean "t5fw_cfg.fwo"
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t5fw_cfg.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw_cfg.txt" \
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compile-with "${CP} ${.ALLSRC} ${.TARGET}" \
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no-obj no-implicit-rule \
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clean "t5fw_cfg.fw"
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t5fw.fwo optional cxgbe \
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dependency "t5fw.fw" \
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compile-with "${NORMAL_FWO}" \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.8.22.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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dev/cy/cy.c optional cy
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dev/cy/cy_isa.c optional cy isa
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dev/cy/cy_pci.c optional cy pci
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@ -67,16 +67,6 @@ enum {
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PAUSE_AUTONEG = 1 << 2
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};
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#define FW_VERSION_MAJOR_T4 1
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#define FW_VERSION_MINOR_T4 8
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#define FW_VERSION_MICRO_T4 4
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#define FW_VERSION_BUILD_T4 0
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#define FW_VERSION_MAJOR_T5 0
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#define FW_VERSION_MINOR_T5 5
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#define FW_VERSION_MICRO_T5 18
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#define FW_VERSION_BUILD_T5 0
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struct memwin {
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uint32_t base;
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uint32_t aperture;
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@ -975,14 +975,14 @@ int t4_check_fw_version(struct adapter *adapter)
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switch (chip_id(adapter)) {
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case CHELSIO_T4:
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exp_major = FW_VERSION_MAJOR_T4;
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exp_minor = FW_VERSION_MINOR_T4;
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exp_micro = FW_VERSION_MICRO_T4;
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exp_major = T4FW_VERSION_MAJOR;
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exp_minor = T4FW_VERSION_MINOR;
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exp_micro = T4FW_VERSION_MICRO;
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break;
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case CHELSIO_T5:
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exp_major = FW_VERSION_MAJOR_T5;
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exp_minor = FW_VERSION_MINOR_T5;
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exp_micro = FW_VERSION_MICRO_T5;
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exp_major = T5FW_VERSION_MAJOR;
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exp_minor = T5FW_VERSION_MINOR;
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exp_micro = T5FW_VERSION_MICRO;
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break;
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default:
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CH_ERR(adapter, "Unsupported chip type, %x\n",
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@ -1128,7 +1128,19 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
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const u32 *p = (const u32 *)fw_data;
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const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
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unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
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unsigned int fw_start_sec;
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unsigned int fw_start;
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unsigned int fw_size;
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if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
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fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
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fw_start = FLASH_FWBOOTSTRAP_START;
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fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
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} else {
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fw_start_sec = FLASH_FW_START_SEC;
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fw_start = FLASH_FW_START;
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fw_size = FLASH_FW_MAX_SIZE;
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}
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if (!size) {
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CH_ERR(adap, "FW image has no data\n");
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return -EINVAL;
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@ -1141,9 +1153,8 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
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CH_ERR(adap, "FW image size differs from size in FW header\n");
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return -EINVAL;
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}
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if (size > FLASH_FW_MAX_SIZE) {
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CH_ERR(adap, "FW image too large, max is %u bytes\n",
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FLASH_FW_MAX_SIZE);
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if (size > fw_size) {
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CH_ERR(adap, "FW image too large, max is %u bytes\n", fw_size);
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return -EFBIG;
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}
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if ((is_t4(adap) && hdr->chip != FW_HDR_CHIP_T4) ||
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@ -1164,8 +1175,7 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
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}
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i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
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ret = t4_flash_erase_sectors(adap, FLASH_FW_START_SEC,
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FLASH_FW_START_SEC + i - 1);
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ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
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if (ret)
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goto out;
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@ -1176,11 +1186,11 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
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*/
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memcpy(first_page, fw_data, SF_PAGE_SIZE);
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((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
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ret = t4_write_flash(adap, FLASH_FW_START, SF_PAGE_SIZE, first_page, 1);
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ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
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if (ret)
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goto out;
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addr = FLASH_FW_START;
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addr = fw_start;
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for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
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addr += SF_PAGE_SIZE;
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fw_data += SF_PAGE_SIZE;
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@ -1190,7 +1200,7 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
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}
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ret = t4_write_flash(adap,
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FLASH_FW_START + offsetof(struct fw_hdr, fw_ver),
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fw_start + offsetof(struct fw_hdr, fw_ver),
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sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
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out:
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if (ret)
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@ -4622,14 +4632,17 @@ int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
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const u8 *fw_data, unsigned int size, int force)
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{
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const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
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unsigned int bootstrap = ntohl(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
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int reset, ret;
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ret = t4_fw_halt(adap, mbox, force);
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if (ret < 0 && !force)
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return ret;
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if (!bootstrap) {
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ret = t4_fw_halt(adap, mbox, force);
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if (ret < 0 && !force)
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return ret;
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}
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ret = t4_load_fw(adap, fw_data, size);
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if (ret < 0)
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if (ret < 0 || bootstrap)
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return ret;
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/*
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@ -230,7 +230,15 @@ enum {
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FLASH_FW_NSECS = 16,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/*
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* Location of bootstrap firmware image in FLASH.
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*/
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FLASH_FWBOOTSTRAP_START_SEC = 27,
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FLASH_FWBOOTSTRAP_NSECS = 1,
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FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
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FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
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/*
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* iSCSI persistent/crash information.
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*/
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@ -248,19 +256,13 @@ enum {
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FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH. Since the FPGA
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* "FLASH" is smaller we need to store the Configuration File in a
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* different location -- which will overlap the end of the firmware
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* image if firmware ever gets that large ...
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* Location of Firmware Configuration File in FLASH.
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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FLASH_FPGA_CFG_START_SEC = 15,
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FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
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/*
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* Sectors 32-63 are reserved for FLASH failover.
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*/
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8417
sys/dev/cxgbe/firmware/t4fw-1.8.11.0.bin.uu
Normal file
8417
sys/dev/cxgbe/firmware/t4fw-1.8.11.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -15,10 +15,14 @@
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sge_timer_value = 1, 5, 10, 50, 100, 200 # usecs
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# TP_SHIFT_CNT
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reg[0x7dc0] = 0x64f8849
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reg[0x7dc0] = 0x62f8849
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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# TP rx and tx channels (0 = auto).
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tp_nrxch = 0
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tp_ntxch = 0
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# TP rx and tx payload memory (% of the total EDRAM + DDR3).
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tp_pmrx = 38
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tp_pmtx = 60
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@ -137,7 +141,7 @@
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[fini]
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version = 0x1
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checksum = 0xfdebb6ef
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checksum = 0x6cc2514b
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#
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# $FreeBSD$
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#
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@ -109,7 +109,7 @@
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reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL
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sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
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reg[0x7dc0] = 0x64f8849 # TP_SHIFT_CNT
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reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT
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# Selection of tuples for LE filter lookup, fields (and widths which
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# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
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@ -124,6 +124,9 @@
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# TP RX payload page size
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tp_pmrx_pagesize = 64K
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# TP number of RX channels
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tp_nrxch = 0 # 0 (auto) = 1
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP TX payload
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tp_pmtx = 50
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@ -131,6 +134,9 @@
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# TP TX payload page size
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tp_pmtx_pagesize = 64K
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# TP number of TX channels
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tp_ntxch = 0 # 0 (auto) = equal number of ports
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# Some "definitions" to make the rest of this a bit more readable. We support
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# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
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# per function per port ...
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@ -514,8 +520,8 @@
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dwm = 30
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[fini]
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version = 0x1425000b
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checksum = 0x7690f7a5
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version = 0x1425000d
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checksum = 0x25c2f782
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -3430,6 +3430,7 @@ enum fw_memtype_cf {
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FW_MEMTYPE_CF_EXTMEM = 0x2,
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FW_MEMTYPE_CF_FLASH = 0x4,
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FW_MEMTYPE_CF_INTERNAL = 0x5,
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FW_MEMTYPE_CF_EXTMEM1 = 0x6,
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};
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struct fw_caps_config_cmd {
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@ -3518,6 +3519,7 @@ enum fw_params_param_dev {
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*/
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FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
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FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
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FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
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};
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/*
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@ -3576,7 +3578,8 @@ enum fw_params_param_dmaq {
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FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
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FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
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FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
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FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13
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FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
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FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
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};
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/*
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@ -3603,6 +3606,7 @@ enum fw_params_phyfw_actions {
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enum fw_params_param_dev_diag {
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FW_PARAM_DEV_DIAG_TMP = 0x00,
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FW_PARAM_DEV_DIAG_VDD = 0x01,
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};
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#define S_FW_PARAMS_MNEM 24
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@ -6767,6 +6771,8 @@ struct fw_sched_cmd {
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__u8 type;
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__u8 minmaxen;
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__u8 r3[5];
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__u8 nclasses[4];
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__be32 r4;
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} config;
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struct fw_sched_params {
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__u8 sc;
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@ -7581,7 +7587,7 @@ struct fw_hdr {
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__u8 intfver_fcoe;
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__u32 reserved2;
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__u32 reserved3;
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__u32 reserved4;
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__u32 magic; /* runtime or bootstrap fw */
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__be32 flags;
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__be32 reserved6[23];
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};
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@ -7620,14 +7626,40 @@ enum fw_hdr_chip {
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(((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
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enum {
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FW_HDR_INTFVER_NIC = 0x00,
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FW_HDR_INTFVER_VNIC = 0x00,
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FW_HDR_INTFVER_OFLD = 0x00,
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FW_HDR_INTFVER_RI = 0x00,
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FW_HDR_INTFVER_ISCSIPDU = 0x00,
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FW_HDR_INTFVER_ISCSI = 0x00,
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FW_HDR_INTFVER_FCOEPDU = 0x00,
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FW_HDR_INTFVER_FCOE = 0x00,
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T4FW_VERSION_MAJOR = 0x01,
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T4FW_VERSION_MINOR = 0x08,
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T4FW_VERSION_MICRO = 0x0b,
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T4FW_VERSION_BUILD = 0x00,
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T5FW_VERSION_MAJOR = 0x01,
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T5FW_VERSION_MINOR = 0x08,
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T5FW_VERSION_MICRO = 0x16,
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T5FW_VERSION_BUILD = 0x00,
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};
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enum {
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T4FW_HDR_INTFVER_NIC = 0x00,
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T4FW_HDR_INTFVER_VNIC = 0x00,
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T4FW_HDR_INTFVER_OFLD = 0x00,
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T4FW_HDR_INTFVER_RI = 0x00,
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T4FW_HDR_INTFVER_ISCSIPDU = 0x00,
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T4FW_HDR_INTFVER_ISCSI = 0x00,
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T4FW_HDR_INTFVER_FCOEPDU = 0x00,
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T4FW_HDR_INTFVER_FCOE = 0x00,
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T5FW_HDR_INTFVER_NIC = 0x00,
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T5FW_HDR_INTFVER_VNIC = 0x00,
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T5FW_HDR_INTFVER_OFLD = 0x00,
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T5FW_HDR_INTFVER_RI = 0x00,
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T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
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T5FW_HDR_INTFVER_ISCSI = 0x00,
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T5FW_HDR_INTFVER_FCOEPDU= 0x00,
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T5FW_HDR_INTFVER_FCOE = 0x00,
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};
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enum {
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FW_HDR_MAGIC_RUNTIME = 0x00000000,
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FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
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};
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enum fw_hdr_flags {
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|
8112
sys/dev/cxgbe/firmware/t5fw-1.8.22.0.bin.uu
Normal file
8112
sys/dev/cxgbe/firmware/t5fw-1.8.22.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
151
sys/dev/cxgbe/firmware/t5fw_cfg.txt
Normal file
151
sys/dev/cxgbe/firmware/t5fw_cfg.txt
Normal file
@ -0,0 +1,151 @@
|
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# Firmware configuration file.
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#
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# Global limits (some are hardware limits, others are due to the firmware).
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# nvi = 128 virtual interfaces
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# niqflint = 1023 ingress queues with freelists and/or interrupts
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# nethctrl = 64K Ethernet or ctrl egress queues
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# neq = 64K egress queues of all kinds, including freelists
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# nexactf = 336 MPS TCAM entries, can oversubscribe.
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#
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|
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[global]
|
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rss_glb_config_mode = basicvirtual
|
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rss_glb_config_options = tnlmapen, hashtoeplitz, tnlalllkp
|
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|
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sge_timer_value = 1, 5, 10, 50, 100, 200 # usecs
|
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|
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# TP_SHIFT_CNT
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reg[0x7dc0] = 0x62f8849
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|
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# TP_GLOBAL_CONFIG
|
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reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
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|
||||
filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# TP rx and tx channels (0 = auto).
|
||||
tp_nrxch = 0
|
||||
tp_ntxch = 0
|
||||
|
||||
# TP rx and tx payload memory (% of the total EDRAM + DDR3).
|
||||
tp_pmrx = 38
|
||||
tp_pmtx = 60
|
||||
tp_pmrx_pagesize = 64K
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
|
||||
# these 4 PFs only. Not used here at all.
|
||||
[function "0"]
|
||||
nvf = 16
|
||||
nvi = 1
|
||||
[function "0/*"]
|
||||
nvi = 1
|
||||
|
||||
[function "1"]
|
||||
nvf = 16
|
||||
nvi = 1
|
||||
[function "1/*"]
|
||||
nvi = 1
|
||||
|
||||
[function "2"]
|
||||
nvf = 16
|
||||
nvi = 1
|
||||
[function "2/*"]
|
||||
nvi = 1
|
||||
|
||||
[function "3"]
|
||||
nvf = 16
|
||||
nvi = 1
|
||||
[function "3/*"]
|
||||
nvi = 1
|
||||
|
||||
# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
|
||||
# It gets 32 MSI/128 MSI-X vectors.
|
||||
[function "4"]
|
||||
wx_caps = all
|
||||
r_caps = all
|
||||
nvi = 32
|
||||
niqflint = 256
|
||||
nethctrl = 128
|
||||
neq = 256
|
||||
nexactf = 328
|
||||
cmask = all
|
||||
pmask = all
|
||||
|
||||
# driver will mask off features it won't use
|
||||
protocol = ofld
|
||||
|
||||
tp_l2t = 4096
|
||||
tp_ddp = 2
|
||||
|
||||
# TCAM has 8K cells; each region must start at a multiple of 128 cell.
|
||||
# Each entry in these categories takes 4 cells each. nhash will use the
|
||||
# TCAM iff there is room left (that is, the rest don't add up to 2048).
|
||||
nroute = 32
|
||||
nclip = 32
|
||||
nfilter = 1008
|
||||
nserver = 512
|
||||
nhash = 16384
|
||||
|
||||
# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
||||
# Not used right now.
|
||||
[function "5"]
|
||||
nvi = 1
|
||||
|
||||
# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
|
||||
# Not used right now.
|
||||
[function "6"]
|
||||
nvi = 1
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
[function "1023"]
|
||||
wx_caps = all
|
||||
r_caps = all
|
||||
nvi = 4
|
||||
cmask = all
|
||||
pmask = all
|
||||
nexactf = 8
|
||||
nfilter = 16
|
||||
|
||||
# MPS has 192K buffer space for ingress packets from the wire as well as
|
||||
# loopback path of the L2 switch.
|
||||
[port "0"]
|
||||
dcb = none
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "1"]
|
||||
dcb = none
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "2"]
|
||||
dcb = none
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "3"]
|
||||
dcb = none
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[fini]
|
||||
version = 0x1
|
||||
checksum = 0xb2417251
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
477
sys/dev/cxgbe/firmware/t5fw_cfg_fpga.txt
Normal file
477
sys/dev/cxgbe/firmware/t5fw_cfg_fpga.txt
Normal file
@ -0,0 +1,477 @@
|
||||
# Chelsio T5 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
|
||||
# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
|
||||
# IN PHYSICAL DAMAGE TO T4 ADAPTERS.
|
||||
|
||||
# This file provides the default, power-on configuration for 4-port T4-based
|
||||
# adapters shipped from the factory. These defaults are designed to address
|
||||
# the needs of the vast majority of T4 customers. The basic idea is to have
|
||||
# a default configuration which allows a customer to plug a T4 adapter in and
|
||||
# have it work regardless of OS, driver or application except in the most
|
||||
# unusual and/or demanding customer applications.
|
||||
#
|
||||
# Many of the T4 resources which are described by this configuration are
|
||||
# finite. This requires balancing the configuration/operation needs of
|
||||
# device drivers across OSes and a large number of customer application.
|
||||
#
|
||||
# Some of the more important resources to allocate and their constaints are:
|
||||
# 1. Virtual Interfaces: 128.
|
||||
# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
|
||||
# must use a power of 2 Ingress Queues.
|
||||
# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
|
||||
# power of 2 Egress Queues.
|
||||
# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
|
||||
# Virtual Functions based off of a Physical Function all get the
|
||||
# same umber of MSI-X Vectors as the base Physical Function.
|
||||
# Additionally, regardless of whether Virtual Functions are enabled or
|
||||
# not, their MSI-X "needs" are counted by the PCI-E implementation.
|
||||
# And finally, all Physical Funcations capable of supporting Virtual
|
||||
# Functions (PF0-3) must have the same number of configured TotalVFs in
|
||||
# their SR-IOV Capabilities.
|
||||
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
|
||||
# address matching on Ingress Packets.
|
||||
#
|
||||
# Some of the important OS/Driver resource needs are:
|
||||
# 6. Some OS Drivers will manage all resources through a single Physical
|
||||
# Function (currently PF0 but it could be any Physical Function). Thus,
|
||||
# this "Unified PF" will need to have enough resources allocated to it
|
||||
# to allow for this. And because of the MSI-X resource allocation
|
||||
# constraints mentioned above, this probably means we'll either have to
|
||||
# severely limit the TotalVFs if we continue to use PF0 as the Unified PF
|
||||
# or we'll need to move the Unified PF into the PF4-7 range since those
|
||||
# Physical Functions don't have any Virtual Functions associated with
|
||||
# them.
|
||||
# 7. Some OS Drivers will manage different ports and functions (NIC,
|
||||
# storage, etc.) on different Physical Functions. For example, NIC
|
||||
# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
|
||||
#
|
||||
# Some of the customer application needs which need to be accommodated:
|
||||
# 8. Some customers will want to support large CPU count systems with
|
||||
# good scaling. Thus, we'll need to accommodate a number of
|
||||
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
|
||||
# to be involved per port and per application function. For example,
|
||||
# in the case where all ports and application functions will be
|
||||
# managed via a single Unified PF and we want to accommodate scaling up
|
||||
# to 8 CPUs, we would want:
|
||||
#
|
||||
# 4 ports *
|
||||
# 3 application functions (NIC, FCoE, iSCSI) per port *
|
||||
# 8 Ingress Queue/MSI-X Vectors per application function
|
||||
#
|
||||
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
|
||||
# (Plus a few for Firmware Event Queues, etc.)
|
||||
#
|
||||
# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
|
||||
# Virtual Machines to directly access T4 functionality via SR-IOV
|
||||
# Virtual Functions and "PCI Device Passthrough" -- this is especially
|
||||
# true for the NIC application functionality. (Note that there is
|
||||
# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual
|
||||
# Functions so this is in fact solely limited to NIC.)
|
||||
#
|
||||
|
||||
|
||||
# Global configuration settings.
|
||||
#
|
||||
[global]
|
||||
rss_glb_config_mode = basicvirtual
|
||||
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
|
||||
|
||||
# PCIE_MA_RSP register
|
||||
pcie_ma_rsp_timervalue = 500 # the timer value in units of us
|
||||
reg[0x59c4] = 0x3/0x3 # enable the timers
|
||||
|
||||
# PL_TIMEOUT register
|
||||
pl_timeout_value = 200 # the timeout value in units of us
|
||||
|
||||
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
|
||||
# Page Size and a 64B L1 Cache Line Size. It programs the
|
||||
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
|
||||
# If a Master PF Driver finds itself on a machine with different
|
||||
# parameters, then the Master PF Driver is responsible for initializing
|
||||
# these parameters to appropriate values.
|
||||
#
|
||||
# Notes:
|
||||
# 1. The Free List Buffer Sizes below are raw and the firmware will
|
||||
# round them up to the Ingress Padding Boundary.
|
||||
# 2. The SGE Timer Values below are expressed below in microseconds.
|
||||
# The firmware will convert these values to Core Clock Ticks when
|
||||
# it processes the configuration parameters.
|
||||
#
|
||||
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
|
||||
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
|
||||
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
|
||||
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
|
||||
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
|
||||
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
|
||||
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
|
||||
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
|
||||
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
|
||||
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
|
||||
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
|
||||
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
|
||||
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
|
||||
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
|
||||
|
||||
# SGE_THROTTLE_CONTROL
|
||||
bar2throttlecount = 500 # bar2throttlecount in us
|
||||
|
||||
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
|
||||
|
||||
|
||||
reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
|
||||
# SGE_VFIFO_SIZE is not set, then
|
||||
# firmware will set it up in function
|
||||
# of number of egress queues used
|
||||
|
||||
reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
|
||||
# threshold set to queue depth
|
||||
# minus 128-entries for FL and HP
|
||||
# queues, and 0xfff for LP which
|
||||
# prompts the firmware to set it up
|
||||
# in function of egress queues
|
||||
# used
|
||||
|
||||
reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
|
||||
# prompts the firmware to set it up in
|
||||
# function of number of egress queues
|
||||
# used
|
||||
|
||||
reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT
|
||||
|
||||
# Selection of tuples for LE filter lookup, fields (and widths which
|
||||
# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
|
||||
# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
|
||||
#
|
||||
filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe, srvrsram
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP RX payload
|
||||
tp_pmrx = 30
|
||||
|
||||
# TP RX payload page size
|
||||
tp_pmrx_pagesize = 64K
|
||||
|
||||
# TP number of RX channels
|
||||
tp_nrxch = 0 # 0 (auto) = 1
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP TX payload
|
||||
tp_pmtx = 50
|
||||
|
||||
# TP TX payload page size
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
#
|
||||
# NMSIX = 1088 # available MSI-X Vectors
|
||||
# NVI = 128 # available Virtual Interfaces
|
||||
# NMPSTCAM = 336 # MPS TCAM entries
|
||||
#
|
||||
# NPORTS = 4 # ports
|
||||
# NCPUS = 8 # CPUs we want to support scalably
|
||||
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
|
||||
|
||||
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
|
||||
# PF" which many OS Drivers will use to manage most or all functions.
|
||||
#
|
||||
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
|
||||
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
|
||||
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
|
||||
# will be specified as the "Ingress Queue Asynchronous Destination Index."
|
||||
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
|
||||
# than or equal to the number of Ingress Queues ...
|
||||
#
|
||||
# NVI_NIC = 4 # NIC access to NPORTS
|
||||
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
|
||||
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
|
||||
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
|
||||
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
|
||||
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_OFLD = 0 # Offload uses NIC function to access ports
|
||||
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
|
||||
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
|
||||
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
|
||||
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
|
||||
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
|
||||
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
|
||||
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
|
||||
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
|
||||
# NETHCTRL_WD = 64 # Wire Direct TX Queues
|
||||
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
|
||||
#
|
||||
# NVI_ISCSI = 4 # ISCSI access to NPORTS
|
||||
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
|
||||
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
|
||||
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
|
||||
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_FCOE = 4 # FCOE access to NPORTS
|
||||
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
|
||||
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
|
||||
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
|
||||
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
|
||||
|
||||
# Two extra Ingress Queues per function for Firmware Events and Forwarded
|
||||
# Interrupts, and two extra interrupts per function for Firmware Events (or a
|
||||
# Forwarded Interrupt Queue) and General Interrupts per function.
|
||||
#
|
||||
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
|
||||
# # Forwarded Interrupts
|
||||
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
|
||||
# # General Interrupts
|
||||
|
||||
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
|
||||
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
|
||||
#
|
||||
# NVI_HYPERV = 16 # VMs we want to support
|
||||
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
|
||||
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
|
||||
# NEQ_HYPERV = 32 # VIQs Free Lists
|
||||
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
|
||||
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
|
||||
|
||||
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
|
||||
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
|
||||
#
|
||||
# NVI_UNIFIED = 28
|
||||
# NFLIQ_UNIFIED = 106
|
||||
# NETHCTRL_UNIFIED = 32
|
||||
# NEQ_UNIFIED = 124
|
||||
# NMPSTCAM_UNIFIED = 40
|
||||
#
|
||||
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
|
||||
# that up to 128 to make sure the Unified PF doesn't run out of resources.
|
||||
#
|
||||
# NMSIX_UNIFIED = 128
|
||||
#
|
||||
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
|
||||
# which is 34 but they're probably safe with 32.
|
||||
#
|
||||
# NMSIX_STORAGE = 32
|
||||
|
||||
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
|
||||
# associated with it. Thus, the MSI-X Vector allocations we give to the
|
||||
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
|
||||
# provision many more Virtual Functions than we can if the UnifiedPF were
|
||||
# one of PF0-3.
|
||||
#
|
||||
|
||||
# All of the below PCI-E parameters are actually stored in various *_init.txt
|
||||
# files. We include them below essentially as comments.
|
||||
#
|
||||
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
|
||||
# ports 0-3.
|
||||
#
|
||||
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
|
||||
#
|
||||
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
|
||||
# storage applications across all four possible ports.
|
||||
#
|
||||
# Additionally, since the UnifiedPF isn't one of the per-port Physical
|
||||
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
|
||||
# different PCI Device IDs which will allow Unified and Per-Port Drivers
|
||||
# to directly select the type of Physical Function to which they wish to be
|
||||
# attached.
|
||||
#
|
||||
# Note that the actual values used for the PCI-E Intelectual Property will be
|
||||
# 1 less than those below since that's the way it "counts" things. For
|
||||
# readability, we use the number we actually mean ...
|
||||
#
|
||||
# PF0_INT = 8 # NCPUS
|
||||
# PF1_INT = 8 # NCPUS
|
||||
# PF2_INT = 8 # NCPUS
|
||||
# PF3_INT = 8 # NCPUS
|
||||
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
|
||||
#
|
||||
# PF4_INT = 128 # NMSIX_UNIFIED
|
||||
# PF5_INT = 32 # NMSIX_STORAGE
|
||||
# PF6_INT = 32 # NMSIX_STORAGE
|
||||
# PF7_INT = 0 # Nothing Assigned
|
||||
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
|
||||
#
|
||||
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
|
||||
#
|
||||
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
|
||||
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
|
||||
#
|
||||
# NVF = 16
|
||||
|
||||
# For those OSes which manage different ports on different PFs, we need
|
||||
# only enough resources to support a single port's NIC application functions
|
||||
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
|
||||
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
|
||||
# managed on the "storage PFs" (see below).
|
||||
#
|
||||
|
||||
# Some OS Drivers manage all application functions for all ports via PF4.
|
||||
# Thus we need to provide a large number of resources here. For Egress
|
||||
# Queues we need to account for both TX Queues as well as Free List Queues
|
||||
# (because the host is responsible for producing Free List Buffers for the
|
||||
# hardware to consume).
|
||||
#
|
||||
[function "0"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 28 # NVI_UNIFIED
|
||||
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
|
||||
nethctrl = 96 # NETHCTRL_UNIFIED + NETHCTRL_WD
|
||||
neq = 252 # NEQ_UNIFIED + NEQ_WD
|
||||
nexactf = 40 # NMPSTCAM_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nroute = 32 # number of routing region entries
|
||||
nclip = 32 # number of clip region entries
|
||||
nfilter = 48 # number of filter region entries
|
||||
nserver = 32 # number of server region entries
|
||||
nhash = 2048 # number of hash region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
tp_stag = 2
|
||||
tp_pbl = 5
|
||||
tp_rq = 7
|
||||
|
||||
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
|
||||
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
|
||||
# "Queue Sets" each.
|
||||
#
|
||||
[function "1"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
|
||||
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
|
||||
# which is OK since < MIN(SUM PF0..3, PF4)
|
||||
# and we never load PF0..3 and PF4 concurrently
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nhash = 2048
|
||||
protocol = fcoe_initiator
|
||||
tp_ddp = 2
|
||||
fcoe_nfcf = 16
|
||||
fcoe_nvnp = 32
|
||||
fcoe_nssn = 1024
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
#
|
||||
[function "1023"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NVI_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nexactf = 8 # NPORTS + DCBX +
|
||||
nfilter = 16 # number of filter region entries
|
||||
|
||||
# For Virtual functions, we only allow NIC functionality and we only allow
|
||||
# access to one port (1 << PF). Note that because of limitations in the
|
||||
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
|
||||
# and GTS registers, the number of Ingress and Egress Queues must be a power
|
||||
# of 2.
|
||||
#
|
||||
[function "0/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
[function "1/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
||||
# for packets from the wire as well as the loopback path of the L2 switch. The
|
||||
# folling params control how the buffer memory is distributed and the L2 flow
|
||||
# control settings:
|
||||
#
|
||||
# bg_mem: %-age of mem to use for port/buffer group
|
||||
# lpbk_mem: %-age of port/bg mem to use for loopback
|
||||
# hwm: high watermark; bytes available when starting to send pause
|
||||
# frames (in units of 0.1 MTU)
|
||||
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
||||
# (in inuits of 0.1 MTU)
|
||||
# dwm: minimum delta between high and low watermark (in units of 100
|
||||
# Bytes)
|
||||
#
|
||||
[port "0"]
|
||||
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "2"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "3"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[fini]
|
||||
version = 0x1425000d
|
||||
checksum = 0xe56cb999
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
# Ingress Queues/w Free Lists and Interrupts: 526
|
||||
# Egress Queues: 702
|
||||
# MPS TCAM Entries: 336
|
||||
# MSI-X Vectors: 736
|
||||
# Virtual Functions: 64
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
568
sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt
Normal file
568
sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt
Normal file
@ -0,0 +1,568 @@
|
||||
# Chelsio T5 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
|
||||
# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
|
||||
# IN PHYSICAL DAMAGE TO T4 ADAPTERS.
|
||||
|
||||
# This file provides the default, power-on configuration for 4-port T4-based
|
||||
# adapters shipped from the factory. These defaults are designed to address
|
||||
# the needs of the vast majority of T4 customers. The basic idea is to have
|
||||
# a default configuration which allows a customer to plug a T4 adapter in and
|
||||
# have it work regardless of OS, driver or application except in the most
|
||||
# unusual and/or demanding customer applications.
|
||||
#
|
||||
# Many of the T4 resources which are described by this configuration are
|
||||
# finite. This requires balancing the configuration/operation needs of
|
||||
# device drivers across OSes and a large number of customer application.
|
||||
#
|
||||
# Some of the more important resources to allocate and their constaints are:
|
||||
# 1. Virtual Interfaces: 128.
|
||||
# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
|
||||
# must use a power of 2 Ingress Queues.
|
||||
# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
|
||||
# power of 2 Egress Queues.
|
||||
# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
|
||||
# Virtual Functions based off of a Physical Function all get the
|
||||
# same umber of MSI-X Vectors as the base Physical Function.
|
||||
# Additionally, regardless of whether Virtual Functions are enabled or
|
||||
# not, their MSI-X "needs" are counted by the PCI-E implementation.
|
||||
# And finally, all Physical Funcations capable of supporting Virtual
|
||||
# Functions (PF0-3) must have the same number of configured TotalVFs in
|
||||
# their SR-IOV Capabilities.
|
||||
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
|
||||
# address matching on Ingress Packets.
|
||||
#
|
||||
# Some of the important OS/Driver resource needs are:
|
||||
# 6. Some OS Drivers will manage all resources through a single Physical
|
||||
# Function (currently PF0 but it could be any Physical Function). Thus,
|
||||
# this "Unified PF" will need to have enough resources allocated to it
|
||||
# to allow for this. And because of the MSI-X resource allocation
|
||||
# constraints mentioned above, this probably means we'll either have to
|
||||
# severely limit the TotalVFs if we continue to use PF0 as the Unified PF
|
||||
# or we'll need to move the Unified PF into the PF4-7 range since those
|
||||
# Physical Functions don't have any Virtual Functions associated with
|
||||
# them.
|
||||
# 7. Some OS Drivers will manage different ports and functions (NIC,
|
||||
# storage, etc.) on different Physical Functions. For example, NIC
|
||||
# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
|
||||
#
|
||||
# Some of the customer application needs which need to be accommodated:
|
||||
# 8. Some customers will want to support large CPU count systems with
|
||||
# good scaling. Thus, we'll need to accommodate a number of
|
||||
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
|
||||
# to be involved per port and per application function. For example,
|
||||
# in the case where all ports and application functions will be
|
||||
# managed via a single Unified PF and we want to accommodate scaling up
|
||||
# to 8 CPUs, we would want:
|
||||
#
|
||||
# 4 ports *
|
||||
# 3 application functions (NIC, FCoE, iSCSI) per port *
|
||||
# 8 Ingress Queue/MSI-X Vectors per application function
|
||||
#
|
||||
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
|
||||
# (Plus a few for Firmware Event Queues, etc.)
|
||||
#
|
||||
# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
|
||||
# Virtual Machines to directly access T4 functionality via SR-IOV
|
||||
# Virtual Functions and "PCI Device Passthrough" -- this is especially
|
||||
# true for the NIC application functionality. (Note that there is
|
||||
# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual
|
||||
# Functions so this is in fact solely limited to NIC.)
|
||||
#
|
||||
|
||||
|
||||
# Global configuration settings.
|
||||
#
|
||||
[global]
|
||||
rss_glb_config_mode = basicvirtual
|
||||
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
|
||||
|
||||
# PL_TIMEOUT register
|
||||
pl_timeout_value = 200 # the timeout value in units of us
|
||||
|
||||
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
|
||||
# Page Size and a 64B L1 Cache Line Size. It programs the
|
||||
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
|
||||
# If a Master PF Driver finds itself on a machine with different
|
||||
# parameters, then the Master PF Driver is responsible for initializing
|
||||
# these parameters to appropriate values.
|
||||
#
|
||||
# Notes:
|
||||
# 1. The Free List Buffer Sizes below are raw and the firmware will
|
||||
# round them up to the Ingress Padding Boundary.
|
||||
# 2. The SGE Timer Values below are expressed below in microseconds.
|
||||
# The firmware will convert these values to Core Clock Ticks when
|
||||
# it processes the configuration parameters.
|
||||
#
|
||||
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
|
||||
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
|
||||
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
|
||||
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
|
||||
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
|
||||
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
|
||||
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
|
||||
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
|
||||
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
|
||||
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
|
||||
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
|
||||
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
|
||||
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
|
||||
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
|
||||
|
||||
# SGE_THROTTLE_CONTROL
|
||||
bar2throttlecount = 500 # bar2throttlecount in us
|
||||
|
||||
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
|
||||
|
||||
|
||||
reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
|
||||
# SGE_VFIFO_SIZE is not set, then
|
||||
# firmware will set it up in function
|
||||
# of number of egress queues used
|
||||
|
||||
reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
|
||||
# threshold set to queue depth
|
||||
# minus 128-entries for FL and HP
|
||||
# queues, and 0xfff for LP which
|
||||
# prompts the firmware to set it up
|
||||
# in function of egress queues
|
||||
# used
|
||||
|
||||
reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
|
||||
# prompts the firmware to set it up in
|
||||
# function of number of egress queues
|
||||
# used
|
||||
|
||||
reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT
|
||||
|
||||
# Selection of tuples for LE filter lookup, fields (and widths which
|
||||
# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
|
||||
# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
|
||||
#
|
||||
filterMode = srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP RX payload
|
||||
tp_pmrx = 30
|
||||
|
||||
# TP RX payload page size
|
||||
tp_pmrx_pagesize = 64K
|
||||
|
||||
# TP number of RX channels
|
||||
tp_nrxch = 0 # 0 (auto) = 1
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP TX payload
|
||||
tp_pmtx = 50
|
||||
|
||||
# TP TX payload page size
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
#
|
||||
# NMSIX = 1088 # available MSI-X Vectors
|
||||
# NVI = 128 # available Virtual Interfaces
|
||||
# NMPSTCAM = 336 # MPS TCAM entries
|
||||
#
|
||||
# NPORTS = 4 # ports
|
||||
# NCPUS = 8 # CPUs we want to support scalably
|
||||
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
|
||||
|
||||
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
|
||||
# PF" which many OS Drivers will use to manage most or all functions.
|
||||
#
|
||||
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
|
||||
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
|
||||
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
|
||||
# will be specified as the "Ingress Queue Asynchronous Destination Index."
|
||||
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
|
||||
# than or equal to the number of Ingress Queues ...
|
||||
#
|
||||
# NVI_NIC = 4 # NIC access to NPORTS
|
||||
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
|
||||
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
|
||||
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
|
||||
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
|
||||
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_OFLD = 0 # Offload uses NIC function to access ports
|
||||
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
|
||||
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
|
||||
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
|
||||
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
|
||||
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
|
||||
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
|
||||
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
|
||||
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
|
||||
# NETHCTRL_WD = 64 # Wire Direct TX Queues
|
||||
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
|
||||
#
|
||||
# NVI_ISCSI = 4 # ISCSI access to NPORTS
|
||||
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
|
||||
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
|
||||
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
|
||||
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_FCOE = 4 # FCOE access to NPORTS
|
||||
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
|
||||
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
|
||||
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
|
||||
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
|
||||
|
||||
# Two extra Ingress Queues per function for Firmware Events and Forwarded
|
||||
# Interrupts, and two extra interrupts per function for Firmware Events (or a
|
||||
# Forwarded Interrupt Queue) and General Interrupts per function.
|
||||
#
|
||||
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
|
||||
# # Forwarded Interrupts
|
||||
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
|
||||
# # General Interrupts
|
||||
|
||||
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
|
||||
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
|
||||
#
|
||||
# NVI_HYPERV = 16 # VMs we want to support
|
||||
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
|
||||
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
|
||||
# NEQ_HYPERV = 32 # VIQs Free Lists
|
||||
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
|
||||
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
|
||||
|
||||
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
|
||||
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
|
||||
#
|
||||
# NVI_UNIFIED = 28
|
||||
# NFLIQ_UNIFIED = 106
|
||||
# NETHCTRL_UNIFIED = 32
|
||||
# NEQ_UNIFIED = 124
|
||||
# NMPSTCAM_UNIFIED = 40
|
||||
#
|
||||
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
|
||||
# that up to 128 to make sure the Unified PF doesn't run out of resources.
|
||||
#
|
||||
# NMSIX_UNIFIED = 128
|
||||
#
|
||||
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
|
||||
# which is 34 but they're probably safe with 32.
|
||||
#
|
||||
# NMSIX_STORAGE = 32
|
||||
|
||||
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
|
||||
# associated with it. Thus, the MSI-X Vector allocations we give to the
|
||||
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
|
||||
# provision many more Virtual Functions than we can if the UnifiedPF were
|
||||
# one of PF0-3.
|
||||
#
|
||||
|
||||
# All of the below PCI-E parameters are actually stored in various *_init.txt
|
||||
# files. We include them below essentially as comments.
|
||||
#
|
||||
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
|
||||
# ports 0-3.
|
||||
#
|
||||
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
|
||||
#
|
||||
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
|
||||
# storage applications across all four possible ports.
|
||||
#
|
||||
# Additionally, since the UnifiedPF isn't one of the per-port Physical
|
||||
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
|
||||
# different PCI Device IDs which will allow Unified and Per-Port Drivers
|
||||
# to directly select the type of Physical Function to which they wish to be
|
||||
# attached.
|
||||
#
|
||||
# Note that the actual values used for the PCI-E Intelectual Property will be
|
||||
# 1 less than those below since that's the way it "counts" things. For
|
||||
# readability, we use the number we actually mean ...
|
||||
#
|
||||
# PF0_INT = 8 # NCPUS
|
||||
# PF1_INT = 8 # NCPUS
|
||||
# PF2_INT = 8 # NCPUS
|
||||
# PF3_INT = 8 # NCPUS
|
||||
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
|
||||
#
|
||||
# PF4_INT = 128 # NMSIX_UNIFIED
|
||||
# PF5_INT = 32 # NMSIX_STORAGE
|
||||
# PF6_INT = 32 # NMSIX_STORAGE
|
||||
# PF7_INT = 0 # Nothing Assigned
|
||||
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
|
||||
#
|
||||
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
|
||||
#
|
||||
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
|
||||
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
|
||||
#
|
||||
# NVF = 16
|
||||
|
||||
# For those OSes which manage different ports on different PFs, we need
|
||||
# only enough resources to support a single port's NIC application functions
|
||||
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
|
||||
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
|
||||
# managed on the "storage PFs" (see below).
|
||||
#
|
||||
[function "0"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port
|
||||
|
||||
[function "1"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port
|
||||
|
||||
[function "2"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x4 # access to only one port
|
||||
|
||||
[function "3"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x8 # access to only one port
|
||||
|
||||
# Some OS Drivers manage all application functions for all ports via PF4.
|
||||
# Thus we need to provide a large number of resources here. For Egress
|
||||
# Queues we need to account for both TX Queues as well as Free List Queues
|
||||
# (because the host is responsible for producing Free List Buffers for the
|
||||
# hardware to consume).
|
||||
#
|
||||
[function "4"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 28 # NVI_UNIFIED
|
||||
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
|
||||
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
|
||||
neq = 256 # NEQ_UNIFIED + NEQ_WD
|
||||
nexactf = 40 # NMPSTCAM_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nethofld = 1024 # number of user mode ethernet flow contexts
|
||||
nroute = 32 # number of routing region entries
|
||||
nclip = 32 # number of clip region entries
|
||||
nfilter = 496 # number of filter region entries
|
||||
nserver = 496 # number of server region entries
|
||||
nhash = 12288 # number of hash region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
tp_stag = 2
|
||||
tp_pbl = 5
|
||||
tp_rq = 7
|
||||
|
||||
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
|
||||
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
|
||||
# "Queue Sets" each.
|
||||
#
|
||||
[function "5"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
|
||||
nexactf = 4 # NPORTS
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nserver = 16
|
||||
nhash = 2048
|
||||
tp_l2t = 1024
|
||||
protocol = iscsi_initiator_fofld
|
||||
tp_ddp_iscsi = 2
|
||||
iscsi_ntask = 2048
|
||||
iscsi_nsess = 2048
|
||||
iscsi_nconn_per_session = 1
|
||||
iscsi_ninitiator_instance = 64
|
||||
|
||||
[function "6"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
|
||||
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
|
||||
# which is OK since < MIN(SUM PF0..3, PF4)
|
||||
# and we never load PF0..3 and PF4 concurrently
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nhash = 2048
|
||||
protocol = fcoe_initiator
|
||||
tp_ddp = 2
|
||||
fcoe_nfcf = 16
|
||||
fcoe_nvnp = 32
|
||||
fcoe_nssn = 1024
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
#
|
||||
[function "1023"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NVI_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nexactf = 8 # NPORTS + DCBX +
|
||||
nfilter = 16 # number of filter region entries
|
||||
|
||||
# For Virtual functions, we only allow NIC functionality and we only allow
|
||||
# access to one port (1 << PF). Note that because of limitations in the
|
||||
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
|
||||
# and GTS registers, the number of Ingress and Egress Queues must be a power
|
||||
# of 2.
|
||||
#
|
||||
[function "0/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
[function "1/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
[function "2/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x4 # access to only one port ...
|
||||
|
||||
[function "3/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x8 # access to only one port ...
|
||||
|
||||
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
||||
# for packets from the wire as well as the loopback path of the L2 switch. The
|
||||
# folling params control how the buffer memory is distributed and the L2 flow
|
||||
# control settings:
|
||||
#
|
||||
# bg_mem: %-age of mem to use for port/buffer group
|
||||
# lpbk_mem: %-age of port/bg mem to use for loopback
|
||||
# hwm: high watermark; bytes available when starting to send pause
|
||||
# frames (in units of 0.1 MTU)
|
||||
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
||||
# (in inuits of 0.1 MTU)
|
||||
# dwm: minimum delta between high and low watermark (in units of 100
|
||||
# Bytes)
|
||||
#
|
||||
[port "0"]
|
||||
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "2"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[port "3"]
|
||||
dcb = ppp, dcbx
|
||||
bg_mem = 25
|
||||
lpbk_mem = 25
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
|
||||
[fini]
|
||||
version = 0x1425000f
|
||||
checksum = 0x23a2d850
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
# Ingress Queues/w Free Lists and Interrupts: 526
|
||||
# Egress Queues: 702
|
||||
# MPS TCAM Entries: 336
|
||||
# MSI-X Vectors: 736
|
||||
# Virtual Functions: 64
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
@ -1826,11 +1826,11 @@ cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
|
||||
}
|
||||
|
||||
#define FW_VERSION(chip) ( \
|
||||
V_FW_HDR_FW_VER_MAJOR(FW_VERSION_MAJOR_##chip) | \
|
||||
V_FW_HDR_FW_VER_MINOR(FW_VERSION_MINOR_##chip) | \
|
||||
V_FW_HDR_FW_VER_MICRO(FW_VERSION_MICRO_##chip) | \
|
||||
V_FW_HDR_FW_VER_BUILD(FW_VERSION_BUILD_##chip))
|
||||
#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
|
||||
V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
|
||||
V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
|
||||
V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
|
||||
V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
|
||||
#define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
|
||||
|
||||
struct fw_info {
|
||||
uint8_t chip;
|
||||
|
@ -4,7 +4,7 @@
|
||||
|
||||
SUBDIR = if_cxgbe
|
||||
SUBDIR+= t4_firmware
|
||||
#SUBDIR+= t5_firmware
|
||||
SUBDIR+= t5_firmware
|
||||
SUBDIR+= ${_tom}
|
||||
|
||||
.if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386"
|
||||
|
@ -17,7 +17,7 @@ FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER = 1.8.4.0
|
||||
T4FW_VER = 1.8.11.0
|
||||
FIRMWS += t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES += t4fw.fw
|
||||
|
||||
|
27
sys/modules/cxgbe/t5_firmware/Makefile
Normal file
27
sys/modules/cxgbe/t5_firmware/Makefile
Normal file
@ -0,0 +1,27 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
T5FW = ${.CURDIR}/../../../dev/cxgbe/firmware
|
||||
.PATH: ${T5FW}
|
||||
|
||||
KMOD = t5fw_cfg
|
||||
FIRMWS = ${KMOD}.txt:${KMOD}:1.0.0.0
|
||||
|
||||
# You can have additional configuration files in the ${T5FW} directory.
|
||||
# t5fw_cfg_<name>.txt
|
||||
CFG_FILES != cd ${T5FW} && echo ${KMOD}_*.txt
|
||||
.for F in ${CFG_FILES}
|
||||
.if exists(${F})
|
||||
FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER = 1.8.22.0
|
||||
FIRMWS += t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES += t5fw.fw
|
||||
|
||||
t5fw.fw: t5fw-${T5FW_VER}.bin.uu
|
||||
uudecode -o ${.TARGET} ${.ALLSRC}
|
||||
|
||||
.include <bsd.kmod.mk>
|
Loading…
Reference in New Issue
Block a user