Split bcm_mipscore.c into bcm_bmips (BMIPS32/BMIPS3300) and bcm_mips74k
drivers. The BMIPS32/BMIPS3300 cores use a register layout distinct from the MIPS74K core, and are only found on siba(4) devices. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D7791
This commit is contained in:
Landon J. Fuller
parent
fd85bff53e
commit
f75615f26f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=305953
@ -68,7 +68,7 @@ static const struct bhnd_core_desc {
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BHND_CDESC(BCM, SRAM, RAM, "SRAM"),
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BHND_CDESC(BCM, SDRAM, RAM, "SDRAM"),
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BHND_CDESC(BCM, PCI, PCI, "PCI Bridge"),
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BHND_CDESC(BCM, MIPS, CPU, "MIPS Core"),
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BHND_CDESC(BCM, MIPS, CPU, "BMIPS CPU"),
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BHND_CDESC(BCM, ENET, ENET_MAC, "Fast Ethernet MAC"),
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BHND_CDESC(BCM, CODEC, OTHER, "V.90 Modem Codec"),
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BHND_CDESC(BCM, USB, USB_DUAL, "USB 1.1 Device/Host Controller"),
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@ -85,7 +85,7 @@ static const struct bhnd_core_desc {
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BHND_CDESC(BCM, APHY, WLAN_PHY, "802.11a PHY"),
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BHND_CDESC(BCM, BPHY, WLAN_PHY, "802.11b PHY"),
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BHND_CDESC(BCM, GPHY, WLAN_PHY, "802.11g PHY"),
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BHND_CDESC(BCM, MIPS33, CPU, "MIPS3302 Core"),
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BHND_CDESC(BCM, MIPS33, CPU, "BMIPS33 CPU"),
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BHND_CDESC(BCM, USB11H, USB_HOST, "USB 1.1 Host Controller"),
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BHND_CDESC(BCM, USB11D, USB_DEV, "USB 1.1 Device Controller"),
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BHND_CDESC(BCM, USB20H, USB_HOST, "USB 2.0 Host Controller"),
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123
sys/mips/broadcom/bcm_bmips.c
Normal file
123
sys/mips/broadcom/bcm_bmips.c
Normal file
@ -0,0 +1,123 @@
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/*-
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/bhnd/bhnd.h>
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#include "bcm_bmipsreg.h"
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/*
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* BMIPS32 and BMIPS3300 core driver.
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*
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* These cores are only found on siba(4) chipsets, allowing
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* us to assume the availability of siba interrupt registers.
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*/
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static const struct bhnd_device bcm_bmips_devs[] = {
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BHND_DEVICE(BCM, MIPS33, NULL, NULL, BHND_DF_SOC),
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BHND_DEVICE_END
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};
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struct bcm_bmips_softc {
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device_t dev;
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struct resource *mem_res;
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int mem_rid;
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};
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static int
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bcm_bmips_probe(device_t dev)
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{
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const struct bhnd_device *id;
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id = bhnd_device_lookup(dev, bcm_bmips_devs,
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sizeof(bcm_bmips_devs[0]));
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if (id == NULL)
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return (ENXIO);
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bhnd_set_default_core_desc(dev);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_bmips_attach(device_t dev)
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{
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struct bcm_bmips_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* Allocate bus resources */
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sc->mem_rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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return (ENXIO);
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return (0);
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}
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static int
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bcm_bmips_detach(device_t dev)
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{
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struct bcm_bmips_softc *sc;
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sc = device_get_softc(dev);
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bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
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return (0);
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}
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static device_method_t bcm_bmips_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, bcm_bmips_probe),
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DEVMETHOD(device_attach, bcm_bmips_attach),
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DEVMETHOD(device_detach, bcm_bmips_detach),
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DEVMETHOD_END
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};
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static devclass_t bcm_mips_devclass;
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DEFINE_CLASS_0(bcm_mips, bcm_bmips_driver, bcm_bmips_methods, sizeof(struct bcm_bmips_softc));
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EARLY_DRIVER_MODULE(bcm_bmips, bhnd, bcm_bmips_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
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MODULE_VERSION(bcm_bmips, 1);
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MODULE_DEPEND(bcm_bmips, bhnd, 1, 1, 1);
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@ -52,8 +52,8 @@
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*
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*********************************************************************/
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#ifndef _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
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#define _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
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#ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
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#define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
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#include <machine/cpufunc.h>
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@ -62,15 +62,15 @@
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* BMIPS330x MIPS32 core.
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*/
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#define MIPS_COP_0_BCMCFG 22
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#define BMIPS_COP_0_BCMCFG 22
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/*
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* Custom CP0 Accessors
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*/
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#define BCM_MIPS_RW32_COP0_SEL(n,r,s) \
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#define BCM_BMIPS_RW32_COP0_SEL(n,r,s) \
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static __inline uint32_t \
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bcm_mips_rd_ ## n(void) \
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bcm_bmips_rd_ ## n(void) \
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{ \
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int v0; \
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__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
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@ -79,7 +79,7 @@ bcm_mips_rd_ ## n(void) \
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return (v0); \
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} \
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static __inline void \
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bcm_mips_wr_ ## n(uint32_t a0) \
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bcm_bmips_wr_ ## n(uint32_t a0) \
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{ \
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__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
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__XSTRING(COP0_SYNC)";" \
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@ -90,101 +90,101 @@ bcm_mips_wr_ ## n(uint32_t a0) \
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mips_barrier(); \
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} struct __hack
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BCM_MIPS_RW32_COP0_SEL(pllcfg1, MIPS_COP_0_CONFIG, 1);
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BCM_MIPS_RW32_COP0_SEL(pllcfg2, MIPS_COP_0_CONFIG, 2);
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BCM_MIPS_RW32_COP0_SEL(clksync, MIPS_COP_0_CONFIG, 3);
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BCM_MIPS_RW32_COP0_SEL(pllcfg3, MIPS_COP_0_CONFIG, 4);
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BCM_MIPS_RW32_COP0_SEL(rstcfg, MIPS_COP_0_CONFIG, 5);
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BCM_BMIPS_RW32_COP0_SEL(pllcfg1, MIPS_COP_0_CONFIG, 1);
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BCM_BMIPS_RW32_COP0_SEL(pllcfg2, MIPS_COP_0_CONFIG, 2);
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BCM_BMIPS_RW32_COP0_SEL(clksync, MIPS_COP_0_CONFIG, 3);
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BCM_BMIPS_RW32_COP0_SEL(pllcfg3, MIPS_COP_0_CONFIG, 4);
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BCM_BMIPS_RW32_COP0_SEL(rstcfg, MIPS_COP_0_CONFIG, 5);
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/*
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* Broadcom PLLConfig1 Register (22, select 1)
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*/
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/* SoftMIPSPLLCfg */
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#define MIPS_BCMCFG_PLLCFG1_MC_SHIFT 10
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#define MIPS_BCMCFG_PLLCFG1_MC_MASK 0xFFFFFC00
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#define BMIPS_BCMCFG_PLLCFG1_MC_SHIFT 10
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#define BMIPS_BCMCFG_PLLCFG1_MC_MASK 0xFFFFFC00
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/* SoftISBPLLCfg */
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#define MIPS_BCMCFG_PLLCFG1_BC_SHIFT 5
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#define MIPS_BCMCFG_PLLCFG1_BC_MASK 0x000003E0
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#define BMIPS_BCMCFG_PLLCFG1_BC_SHIFT 5
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#define BMIPS_BCMCFG_PLLCFG1_BC_MASK 0x000003E0
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/* SoftRefPLLCfg */
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#define MIPS_BCMCFG_PLLCFG1_PC_SHIFT 0
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#define MIPS_BCMCFG_PLLCFG1_PC_MASK 0x0000001F
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#define BMIPS_BCMCFG_PLLCFG1_PC_SHIFT 0
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#define BMIPS_BCMCFG_PLLCFG1_PC_MASK 0x0000001F
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/*
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* Broadcom PLLConfig2 Register (22, select 2)
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*/
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/* Soft1to1ClkRatio */
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#define MIPS_BCMCFG_PLLCFG2_CR (1<<23)
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#define BMIPS_BCMCFG_PLLCFG2_CR (1<<23)
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/* SoftUSBxPLLCfg */
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#define MIPS_BCMCFG_PLLCFG2_UC_SHIFT 15
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#define MIPS_BCMCFG_PLLCFG2_UC_MASK 0x007F8000
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#define BMIPS_BCMCFG_PLLCFG2_UC_SHIFT 15
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#define BMIPS_BCMCFG_PLLCFG2_UC_MASK 0x007F8000
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/* SoftIDExPLLCfg */
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#define MIPS_BCMCFG_PLLCFG2_IC_SHIFT 7
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#define MIPS_BCMCFG_PLLCFG2_IC_MASK 0x00007F80
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#define BMIPS_BCMCFG_PLLCFG2_IC_SHIFT 7
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#define BMIPS_BCMCFG_PLLCFG2_IC_MASK 0x00007F80
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#define MIPS_BCMCFG_PLLCFG2_BE (1<<6) /* ISBxSoftCfgEnable */
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#define MIPS_BCMCFG_PLLCFG2_UE (1<<5) /* USBxSoftCfgEnable */
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#define MIPS_BCMCFG_PLLCFG2_IE (1<<4) /* IDExSoftCfgEnable */
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#define MIPS_BCMCFG_PLLCFG2_CA (1<<3) /* CfgActive */
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#define MIPS_BCMCFG_PLLCFG2_CF (1<<2) /* RefSoftCfgEnable */
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#define MIPS_BCMCFG_PLLCFG2_CI (1<<1) /* ISBSoftCfgEnable */
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#define MIPS_BCMCFG_PLLCFG2_CC (1<<0) /* MIPSSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_BE (1<<6) /* ISBxSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_UE (1<<5) /* USBxSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_IE (1<<4) /* IDExSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CA (1<<3) /* CfgActive */
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#define BMIPS_BCMCFG_PLLCFG2_CF (1<<2) /* RefSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CI (1<<1) /* ISBSoftCfgEnable */
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#define BMIPS_BCMCFG_PLLCFG2_CC (1<<0) /* MIPSSoftCfgEnable */
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/*
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* Broadcom ClkSync Register (22, select 3)
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*/
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/* SoftClkCfgHigh */
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#define MIPS_BCMCFG_CLKSYNC_CH_SHIFT 16
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#define MIPS_BCMCFG_CLKSYNC_CH_MASK 0xFFFF0000
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#define BMIPS_BCMCFG_CLKSYNC_CH_SHIFT 16
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#define BMIPS_BCMCFG_CLKSYNC_CH_MASK 0xFFFF0000
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/* SoftClkCfgLow */
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#define MIPS_BCMCFG_CLKSYNC_CL_SHIFT 0
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#define MIPS_BCMCFG_CLKSYNC_CL_MASK 0x0000FFFF
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#define BMIPS_BCMCFG_CLKSYNC_CL_SHIFT 0
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#define BMIPS_BCMCFG_CLKSYNC_CL_MASK 0x0000FFFF
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/*
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* Broadcom ISBxPLLConfig3 Register (22, select 4)
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*/
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/* AsyncClkRatio */
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#define MIPS_BCMCFG_PLLCFG3_AR_SHIFT 23
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#define MIPS_BCMCFG_PLLCFG3_AR_MASK 0x01800000
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#define BMIPS_BCMCFG_PLLCFG3_AR_SHIFT 23
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#define BMIPS_BCMCFG_PLLCFG3_AR_MASK 0x01800000
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#define MIPS_BCMCFG_PLLCFG3_SM (1<<22) /* SyncMode */
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#define BMIPS_BCMCFG_PLLCFG3_SM (1<<22) /* SyncMode */
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/* SoftISBxPLLCfg */
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#define MIPS_BCMCFG_PLLCFG3_IC_SHIFT 0
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#define MIPS_BCMCFG_PLLCFG3_IC_MASK 0x003FFFFF
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#define BMIPS_BCMCFG_PLLCFG3_IC_SHIFT 0
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#define BMIPS_BCMCFG_PLLCFG3_IC_MASK 0x003FFFFF
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/*
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* Broadcom BRCMRstConfig Register (22, select 5)
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*/
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#define MIPS_BCMCFG_RSTCFG_SR (1<<18) /* SSMR */
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#define MIPS_BCMCFG_RSTCFG_DT (1<<16) /* BHTD */
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#define BMIPS_BCMCFG_RSTCFG_SR (1<<18) /* SSMR */
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#define BMIPS_BCMCFG_RSTCFG_DT (1<<16) /* BHTD */
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/* RStSt */
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#define MIPS_BCMCFG_RSTCFG_RS_SHIFT 8
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#define MIPS_BCMCFG_RSTCFG_RS_MASK 0x00001F00
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#define MIPS_BCMCFG_RST_OTHER 0x00
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#define MIPS_BCMCFG_RST_SH 0x01
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#define MIPS_BCMCFG_RST_SS 0x02
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#define MIPS_BCMCFG_RST_EJTAG 0x04
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#define MIPS_BCMCFG_RST_WDOG 0x08
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#define MIPS_BCMCFG_RST_CRC 0x10
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#define BMIPS_BCMCFG_RSTCFG_RS_SHIFT 8
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#define BMIPS_BCMCFG_RSTCFG_RS_MASK 0x00001F00
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#define BMIPS_BCMCFG_RST_OTHER 0x00
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#define BMIPS_BCMCFG_RST_SH 0x01
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#define BMIPS_BCMCFG_RST_SS 0x02
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#define BMIPS_BCMCFG_RST_EJTAG 0x04
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#define BMIPS_BCMCFG_RST_WDOG 0x08
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#define BMIPS_BCMCFG_RST_CRC 0x10
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#define MIPS_BCMCFG_RSTCFG_CR (1<<7) /* RStCr */
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#define BMIPS_BCMCFG_RSTCFG_CR (1<<7) /* RStCr */
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/* WBMD */
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#define MIPS_BCMCFG_RSTCFG_WD_SHIFT 3
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#define MIPS_BCMCFG_RSTCFG_WD_MASK 0x00000078
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#define BMIPS_BCMCFG_RSTCFG_WD_SHIFT 3
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#define BMIPS_BCMCFG_RSTCFG_WD_MASK 0x00000078
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#define MIPS_BCMCFG_RSTCFG_SS (1<<2) /* SSR */
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#define MIPS_BCMCFG_RSTCFG_SH (1<<1) /* SHR */
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#define MIPS_BCMCFG_RSTCFG_BR (1<<0) /* BdR */
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#define BMIPS_BCMCFG_RSTCFG_SS (1<<2) /* SSR */
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#define BMIPS_BCMCFG_RSTCFG_SH (1<<1) /* SHR */
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#define BMIPS_BCMCFG_RSTCFG_BR (1<<0) /* BdR */
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#endif /* _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ */
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#endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */
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73
sys/mips/broadcom/bcm_bmipsreg.h
Normal file
73
sys/mips/broadcom/bcm_bmipsreg.h
Normal file
@ -0,0 +1,73 @@
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/*-
|
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* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
|
||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
|
||||
* redistribution must be conditioned upon including a substantially
|
||||
* similar Disclaimer requirement for further binary redistribution.
|
||||
*
|
||||
* NO WARRANTY
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
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#ifndef _MIPS_BROADCOM_BMIPSREG_H_
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#define _MIPS_BROADCOM_BMIPSREG_H_
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/*
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* Common BMIPS32/BMIPS3300 Registers
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*/
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#define BCM_BMIPS_CORECTL 0x00 /**< core control */
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#define BCM_BMIPS_CORECTL_FORCE_RST 0x01 /**< force reset */
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#define BCM_BMIPS_CORECTL_NO_FLSH_EXC 0x02 /**< flash exception disable */
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#define BCM_BMIPS_INTR_STATUS 0x20 /**< interrupt status */
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#define BCM_BMIPS_INTR_MASK 0x24 /**< interrupt mask */
|
||||
#define BCM_BMIPS_TIMER_INTMASK 0x01 /**< timer interrupt mask */
|
||||
#define BCM_BMIPS_TIMER_CTRL 0x28 /**< timer interval (?) */
|
||||
|
||||
/*
|
||||
* Broadcom BMIPS32 (BHND_COREID_MIPS)
|
||||
*/
|
||||
|
||||
#define BCM_BMIPS32_CORECTL BCM_BMIPS_CORECTL
|
||||
#define BCM_BMIPS32_BIST_STATUS 0x04 /**< built-in self-test status */
|
||||
#define BCM_BMIPS32_INTR_STATUS BCM_BMIPS_INTR_STATUS
|
||||
#define BCM_BMIPS32_INTR_MASK BCM_BMIPS_INTR_MASK
|
||||
#define BCM_BMIPS32_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
|
||||
|
||||
/*
|
||||
* Broadcom BMIPS3300+ (BHND_COREID_MIPS33)
|
||||
*/
|
||||
|
||||
#define BCM_BMIPS33_CORECTL BCM_BMIPS_CORECTL
|
||||
#define BCM_BMIPS33_BIST_CTRL 0x04 /**< build-in self-test control */
|
||||
#define BCM_BMIPS33_BIST_CTRL_DUMP 0x01 /**< BIST dump */
|
||||
#define BCM_BMIPS33_BIST_CTRL_DEBUG 0x02 /**< BIST debug */
|
||||
#define BCM_BMIPS33_BIST_CTRL_HOLD 0x04 /**< BIST hold */
|
||||
#define BCM_BMIPS33_BIST_STATUS 0x08 /**< built-in self-test status */
|
||||
#define BCM_BMIPS33_INTR_STATUS BCM_BMIPS_INTR_STATUS
|
||||
#define BCM_BMIPS33_INTR_MASK BCM_BMIPS_INTR_MASK
|
||||
#define BCM_BMIPS33_TIMER_CTRL BCM_BMIPS_TIMER_CTRL
|
||||
#define BCM_BMIPS33_TEST_MUX_SEL 0x30 /**< test multiplexer select (?) */
|
||||
#define BCM_BMIPS33_TEST_MUX_EN 0x34 /**< test multiplexer enable (?) */
|
||||
#define BCM_BMIPS33_EJTAG_GPIO_EN 0x2C /**< ejtag gpio enable */
|
||||
|
||||
#endif /* _MIPS_BROADCOM_BMIPSREG_H_ */
|
||||
@ -84,7 +84,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
|
||||
|
||||
#include "bcm_machdep.h"
|
||||
#include "bcm_mips_exts.h"
|
||||
#include "bcm_bmips_exts.h"
|
||||
|
||||
#ifdef CFE
|
||||
#include <dev/cfe/cfe_api.h>
|
||||
@ -436,7 +436,7 @@ platform_reset(void)
|
||||
bcm4785war = true;
|
||||
|
||||
/* Switch to async mode */
|
||||
bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM);
|
||||
bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM);
|
||||
}
|
||||
|
||||
/* Set watchdog (PMU or ChipCommon) */
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
/*-
|
||||
* Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
|
||||
* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -34,41 +35,40 @@ __FBSDID("$FreeBSD$");
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/stddef.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include <machine/resource.h>
|
||||
|
||||
#include <dev/bhnd/bhnd.h>
|
||||
#include <dev/bhnd/bhndvar.h>
|
||||
#include <dev/bhnd/bhnd_ids.h>
|
||||
|
||||
#include "bcm_mipscore.h"
|
||||
#include "bcm_mips74kreg.h"
|
||||
|
||||
static const struct resource_spec mipscore_rspec[MIPSCORE_MAX_RSPEC] = {
|
||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
|
||||
{ -1, -1, 0 }
|
||||
};
|
||||
/*
|
||||
* Broadcom MIPS74K Core
|
||||
*
|
||||
* These cores are only found on bcma(4) chipsets, allowing
|
||||
* us to assume the availability of bcma interrupt registers.
|
||||
*/
|
||||
|
||||
#define MIPSCORE_DEV(_vendor, _core) \
|
||||
BHND_DEVICE(_vendor, _core, NULL, NULL, BHND_DF_SOC)
|
||||
|
||||
struct bhnd_device mipscore_match[] = {
|
||||
MIPSCORE_DEV(BCM, MIPS),
|
||||
MIPSCORE_DEV(BCM, MIPS33),
|
||||
MIPSCORE_DEV(MIPS, MIPS74K),
|
||||
static const struct bhnd_device bcm_mips74k_devs[] = {
|
||||
BHND_DEVICE(MIPS, MIPS74K, NULL, NULL, BHND_DF_SOC),
|
||||
BHND_DEVICE_END
|
||||
};
|
||||
|
||||
static int
|
||||
mipscore_probe(device_t dev)
|
||||
{
|
||||
const struct bhnd_device *id;
|
||||
struct bcm_mips74k_softc {
|
||||
device_t dev;
|
||||
struct resource *mem_res;
|
||||
int mem_rid;
|
||||
};
|
||||
|
||||
id = bhnd_device_lookup(dev, mipscore_match, sizeof(mipscore_match[0]));
|
||||
static int
|
||||
bcm_mips74k_probe(device_t dev)
|
||||
{
|
||||
const struct bhnd_device *id;
|
||||
|
||||
id = bhnd_device_lookup(dev, bcm_mips74k_devs,
|
||||
sizeof(bcm_mips74k_devs[0]));
|
||||
if (id == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
@ -77,50 +77,51 @@ mipscore_probe(device_t dev)
|
||||
}
|
||||
|
||||
static int
|
||||
mipscore_attach(device_t dev)
|
||||
bcm_mips74k_attach(device_t dev)
|
||||
{
|
||||
struct mipscore_softc *sc;
|
||||
struct resource *res;
|
||||
uint32_t intmask;
|
||||
uint16_t devid;
|
||||
int error;
|
||||
struct bcm_mips74k_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
devid = bhnd_get_device(dev);
|
||||
|
||||
sc->devid = devid;
|
||||
sc->dev = dev;
|
||||
|
||||
/* Allocate bus resources */
|
||||
memcpy(sc->rspec, mipscore_rspec, sizeof(sc->rspec));
|
||||
error = bhnd_alloc_resources(dev, sc->rspec, sc->res);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
res = sc->res[0]->res;
|
||||
if (res == NULL)
|
||||
sc->mem_rid = 0;
|
||||
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
|
||||
RF_ACTIVE);
|
||||
if (sc->mem_res == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
if (devid == BHND_COREID_MIPS74K) {
|
||||
intmask = (1 << 31);
|
||||
/* Use intmask5 register to route the timer interrupt */
|
||||
bus_write_4(res, offsetof(struct mipscore_regs, intmask[5]),
|
||||
intmask);
|
||||
}
|
||||
/* Route MIPS timer to IRQ5 */
|
||||
bus_write_4(sc->mem_res, BCM_MIPS74K_INTR5_SEL,
|
||||
(1<<BCM_MIPS74K_TIMER_IVEC));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t mipscore_methods[] = {
|
||||
DEVMETHOD(device_probe, mipscore_probe),
|
||||
DEVMETHOD(device_attach, mipscore_attach),
|
||||
DEVMETHOD_END
|
||||
static int
|
||||
bcm_mips74k_detach(device_t dev)
|
||||
{
|
||||
struct bcm_mips74k_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t bcm_mips74k_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, bcm_mips74k_probe),
|
||||
DEVMETHOD(device_attach, bcm_mips74k_attach),
|
||||
DEVMETHOD(device_detach, bcm_mips74k_detach),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
devclass_t bhnd_mipscore_devclass;
|
||||
static devclass_t bcm_mips_devclass;
|
||||
|
||||
DEFINE_CLASS_0(bhnd_mips, mipscore_driver, mipscore_methods,
|
||||
sizeof(struct mipscore_softc));
|
||||
EARLY_DRIVER_MODULE(bhnd_mips, bhnd, mipscore_driver,
|
||||
bhnd_mipscore_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
|
||||
MODULE_VERSION(bhnd_mips, 1);
|
||||
DEFINE_CLASS_0(bcm_mips, bcm_mips74k_driver, bcm_mips74k_methods, sizeof(struct bcm_mips74k_softc));
|
||||
EARLY_DRIVER_MODULE(bcm_mips74k, bhnd, bcm_mips74k_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
|
||||
MODULE_VERSION(bcm_mips74k, 1);
|
||||
MODULE_DEPEND(bcm_mips74k, bhnd, 1, 1, 1);
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
|
||||
* Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -25,36 +25,38 @@
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _BHND_CORES_MIPS_MIPSCOREVAR_H_
|
||||
#define _BHND_CORES_MIPS_MIPSCOREVAR_H_
|
||||
#ifndef _MIPS_BROADCOM_MIPS74KREG_H_
|
||||
#define _MIPS_BROADCOM_MIPS74KREG_H_
|
||||
|
||||
#define MIPSCORE_MAX_RSPEC 2
|
||||
#define BCM_MIPS74K_CORECTL 0x00 /**< core control */
|
||||
#define BCM_MIPS74K_EXCBASE 0x04 /**< exception base */
|
||||
|
||||
struct mipscore_softc {
|
||||
device_t dev; /* CPU device */
|
||||
uint32_t devid;
|
||||
struct resource_spec rspec[MIPSCORE_MAX_RSPEC];
|
||||
struct bhnd_resource *res[MIPSCORE_MAX_RSPEC];
|
||||
};
|
||||
#define BCM_MIPS74K_BIST_STATUS 0x0C /**< built-in self-test status */
|
||||
#define BCM_MIPS74K_INTR_STATUS 0x10 /**< interrupt status */
|
||||
|
||||
struct mipscore_regs {
|
||||
uint32_t corecontrol;
|
||||
uint32_t exceptionbase;
|
||||
uint32_t PAD1[1]; /* unmapped address */
|
||||
uint32_t biststatus;
|
||||
uint32_t intstatus;
|
||||
uint32_t intmask[6];
|
||||
uint32_t nmimask;
|
||||
uint32_t PAD2[4]; /* unmapped addresses */
|
||||
uint32_t gpioselect;
|
||||
uint32_t gpiooutput;
|
||||
uint32_t gpioenable;
|
||||
uint32_t PAD3[101]; /* unmapped addresses */
|
||||
uint32_t clkcontrolstatus;
|
||||
};
|
||||
/* INTR(0-5)_MASK map bcma(4) OOB interrupt bus lines to MIPS hardware
|
||||
* interrupts. */
|
||||
#define BCM_MIPS74K_INTR0_SEL 0x14 /**< IRQ0 OOBSEL mask */
|
||||
#define BCM_MIPS74K_INTR1_SEL 0x18 /**< IRQ1 OOBSEL mask */
|
||||
#define BCM_MIPS74K_INTR2_SEL 0x1C /**< IRQ2 OOBSEL mask */
|
||||
#define BCM_MIPS74K_INTR3_SEL 0x20 /**< IRQ3 OOBSEL mask */
|
||||
#define BCM_MIPS74K_INTR4_SEL 0x24 /**< IRQ4 OOBSEL mask */
|
||||
#define BCM_MIPS74K_INTR5_SEL 0x28 /**< IRQ5 OOBSEL mask */
|
||||
|
||||
#endif /* _BHND_CORES_MIPS_MIPSCOREVAR_H_ */
|
||||
#define BCM_MIPS74K_INTR_SEL(_intr) \
|
||||
(BCM_MIPS74K_INTR0_SEL + ((_intr) * 4))
|
||||
|
||||
#define BCM_MIPS74K_NMI_MASK 0x2C /**< nmi mask */
|
||||
|
||||
#define BCM_MIPS74K_GPIO_SEL 0x40 /**< gpio select */
|
||||
#define BCM_MIPS74K_GPIO_OUT 0x44 /**< gpio output enable */
|
||||
#define BCM_MIPS74K_GPIO_EN 0x48 /**< gpio enable */
|
||||
|
||||
|
||||
#define BCM_MIPS74K_TIMER_IVEC 31 /**< MIPS timer OOBSEL value */
|
||||
|
||||
#endif /* _MIPS_BROADCOM_MIPS74KREG_H_ */
|
||||
@ -5,6 +5,8 @@
|
||||
# which are believed to be devices we have drivers for
|
||||
# which just need to be tweaked for attachment to an BHND system bus.
|
||||
mips/broadcom/bcm_machdep.c standard
|
||||
mips/broadcom/bcm_bmips.c optional siba_nexus siba
|
||||
mips/broadcom/bcm_mips74k.c optional bcma_nexus bcma
|
||||
mips/broadcom/bcm_pmu.c standard
|
||||
mips/mips/tick.c standard
|
||||
mips/mips/mips_pic.c standard
|
||||
@ -15,7 +17,6 @@ kern/msi_if.m optional intrng
|
||||
|
||||
mips/broadcom/uart_cpu_chipc.c optional uart
|
||||
mips/broadcom/uart_bus_chipc.c optional uart
|
||||
mips/broadcom/bcm_mipscore.c standard
|
||||
|
||||
# TODO: Replace with BCM47xx/57xx/etc-aware geom_map
|
||||
geom/geom_flashmap.c standard
|
||||
@ -23,4 +24,4 @@ geom/geom_flashmap.c standard
|
||||
# USB bits
|
||||
dev/bhnd/cores/usb/bhnd_usb.c optional usb
|
||||
dev/bhnd/cores/usb/bhnd_ehci.c optional ehci
|
||||
dev/bhnd/cores/usb/bhnd_ohci.c optional ohci
|
||||
dev/bhnd/cores/usb/bhnd_ohci.c optional ohci
|
||||
|
||||
Loading…
Reference in New Issue
Block a user