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Configure the analog input 7 which, on BBB, is connected to the 3V3B rail

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through a voltage divisor (R163 and R164 on page 4 of BBB schematic).

Add a note about this on ti_adc(4) man page.  The ti_adc(4) man page will
first appear on 10.1-RELEASE.

MFC after:	1 week
Suggested by:	Sulev-Madis Silber (ketas)
Manual page reviewed by:	brueffer (D127)
This commit is contained in:
Luiz Otavio O Souza 2014-06-02 02:00:17 +00:00
parent ebfbfab668
commit f7eebb7730
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=266960
4 changed files with 17 additions and 5 deletions
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15
share/man/man4/man4.arm/ti_adc.4
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@ -24,7 +24,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd March 21, 2014
.Dd June 1, 2014
.Dt TI_ADC 4
.Os
.Sh NAME
@ -78,8 +78,17 @@ dev.ti_adc.0.ain.6.enable: 1
dev.ti_adc.0.ain.6.open_delay: 0
dev.ti_adc.0.ain.6.samples_avg: 4
dev.ti_adc.0.ain.6.input: 2308
dev.ti_adc.0.ain.7.enable: 1
dev.ti_adc.0.ain.7.open_delay: 0
dev.ti_adc.0.ain.7.samples_avg: 0
dev.ti_adc.0.ain.7.input: 3812
.Ed
.Pp
On Beaglebone-black the analog input 7 is connected to the 3V3B rail through
a voltage divisor (2:1).
The 3V3B voltage rail comes from the TL5209 LDO regulator which is limited
to 500mA maximum.
.Pp
Global settings:
.Bl -tag -width ".Va dev.ti_adc.0.clockdiv"
.It Va dev.ti_adc.0.clockdiv
@ -112,8 +121,8 @@ It is made of a 12 bit value (0 ~ 4095).
The
.Nm
driver first appeared in
.Fx 11.0 .
.Fx 10.1 .
.Sh AUTHORS
.An -nosplit
The driver and this manual page was written by
.An Luiz Otavio O Souza Aq loos@FreeBSD.org
.An Luiz Otavio O Souza Aq loos@FreeBSD.org .

3
sys/arm/ti/ti_adc.c
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@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
#include <arm/ti/ti_adcreg.h>
#include <arm/ti/ti_adcvar.h>
/* Define our 7 steps, one for each input channel. */
/* Define our 8 steps, one for each input channel. */
static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
{ .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 },
{ .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 },
@ -59,6 +59,7 @@ static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
{ .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 },
{ .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 },
{ .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 },
{ .stepconfig = ADC_STEPCFG8, .stepdelay = ADC_STEPDLY8 },
};
static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };

2
sys/arm/ti/ti_adcreg.h
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@ -81,6 +81,8 @@
#define ADC_STEPDLY6 0x090
#define ADC_STEPCFG7 0x094
#define ADC_STEPDLY7 0x098
#define ADC_STEPCFG8 0x09c
#define ADC_STEPDLY8 0x0a0
#define ADC_STEP_DIFF_CNTRL (1 << 25)
#define ADC_STEP_RFM_MSK 0x01800000
#define ADC_STEP_RFM_SHIFT 23

2
sys/arm/ti/ti_adcvar.h
View File

@ -29,7 +29,7 @@
#ifndef _TI_ADCVAR_H_
#define _TI_ADCVAR_H_
#define TI_ADC_NPINS 7
#define TI_ADC_NPINS 8
#define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg)
#define ADC_WRITE4(_sc, reg, value) \