Configure the analog input 7 which, on BBB, is connected to the 3V3B rail
through a voltage divisor (R163 and R164 on page 4 of BBB schematic). Add a note about this on ti_adc(4) man page. The ti_adc(4) man page will first appear on 10.1-RELEASE. MFC after: 1 week Suggested by: Sulev-Madis Silber (ketas) Manual page reviewed by: brueffer (D127)
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2020-12-20 02:59:44 +00:00
svn path=/head/; revision=266960
@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 21, 2014
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.Dd June 1, 2014
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.Dt TI_ADC 4
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.Os
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.Sh NAME
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@ -78,8 +78,17 @@ dev.ti_adc.0.ain.6.enable: 1
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dev.ti_adc.0.ain.6.open_delay: 0
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dev.ti_adc.0.ain.6.samples_avg: 4
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dev.ti_adc.0.ain.6.input: 2308
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dev.ti_adc.0.ain.7.enable: 1
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dev.ti_adc.0.ain.7.open_delay: 0
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dev.ti_adc.0.ain.7.samples_avg: 0
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dev.ti_adc.0.ain.7.input: 3812
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.Ed
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.Pp
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On Beaglebone-black the analog input 7 is connected to the 3V3B rail through
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a voltage divisor (2:1).
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The 3V3B voltage rail comes from the TL5209 LDO regulator which is limited
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to 500mA maximum.
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.Pp
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Global settings:
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.Bl -tag -width ".Va dev.ti_adc.0.clockdiv"
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.It Va dev.ti_adc.0.clockdiv
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@ -112,8 +121,8 @@ It is made of a 12 bit value (0 ~ 4095).
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The
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.Nm
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driver first appeared in
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.Fx 11.0 .
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.Fx 10.1 .
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.Sh AUTHORS
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.An -nosplit
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The driver and this manual page was written by
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.An Luiz Otavio O Souza Aq loos@FreeBSD.org
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.An Luiz Otavio O Souza Aq loos@FreeBSD.org .
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@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
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#include <arm/ti/ti_adcreg.h>
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#include <arm/ti/ti_adcvar.h>
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/* Define our 7 steps, one for each input channel. */
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/* Define our 8 steps, one for each input channel. */
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static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
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{ .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 },
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{ .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 },
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@ -59,6 +59,7 @@ static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
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{ .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 },
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{ .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 },
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{ .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 },
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{ .stepconfig = ADC_STEPCFG8, .stepdelay = ADC_STEPDLY8 },
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};
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static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
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@ -81,6 +81,8 @@
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#define ADC_STEPDLY6 0x090
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#define ADC_STEPCFG7 0x094
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#define ADC_STEPDLY7 0x098
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#define ADC_STEPCFG8 0x09c
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#define ADC_STEPDLY8 0x0a0
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#define ADC_STEP_DIFF_CNTRL (1 << 25)
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#define ADC_STEP_RFM_MSK 0x01800000
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#define ADC_STEP_RFM_SHIFT 23
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@ -29,7 +29,7 @@
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#ifndef _TI_ADCVAR_H_
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#define _TI_ADCVAR_H_
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#define TI_ADC_NPINS 7
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#define TI_ADC_NPINS 8
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#define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg)
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#define ADC_WRITE4(_sc, reg, value) \
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