Add a driver for SMI-based SpeedStep. The hardware supports two frequency
settings and is an older version of the same design used for ICH SpeedStep. It is only known to be available on PIIX4 chipsets. Many thanks to Bruno Ducrot for writing the driver and Jon Noack for testing. Submitted by: Bruno Ducrot
This commit is contained in:
Nate Lawson
parent
265cd33757
commit
f8420b5828
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=145287
@ -107,6 +107,8 @@ Intel Enhanced SpeedStep
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Intel SpeedStep for ICH
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.It Pa powernow
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AMD PowerNow! for K7 and K8
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.It Pa smist
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Intel SMI-based SpeedStep for PIIX4
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.El
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.Pp
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The following device drivers offer relative frequency control and
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460
sys/i386/cpufreq/smist.c
Normal file
460
sys/i386/cpufreq/smist.c
Normal file
@ -0,0 +1,460 @@
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/*-
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* Copyright (c) 2005 Bruno Ducrot
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This driver is based upon information found by examining speedstep-0.5
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* from Marc Lehman, which includes all the reverse engineering effort of
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* Malik Martin (function 1 and 2 of the GSI).
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*
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* The correct way for the OS to take ownership from the BIOS was found by
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* Hiroshi Miura (function 0 of the GSI).
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*
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* Finally, the int 15h call interface was (partially) documented by Intel.
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*
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* Many thanks to Jon Noack for testing and debugging this driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <machine/md_var.h>
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#include <machine/vm86.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include "cpufreq_if.h"
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#if 0
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#define DPRINT(dev, x...) device_printf(dev, x)
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#else
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#define DPRINT(dev, x...)
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#endif
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struct smist_softc {
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device_t dev;
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int smi_cmd;
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int smi_data;
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int command;
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int flags;
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struct cf_setting sets[2]; /* Only two settings. */
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};
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static void smist_identify(driver_t *driver, device_t parent);
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static int smist_probe(device_t dev);
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static int smist_attach(device_t dev);
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static int smist_detach(device_t dev);
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static int smist_settings(device_t dev, struct cf_setting *sets,
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int *count);
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static int smist_set(device_t dev, const struct cf_setting *set);
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static int smist_get(device_t dev, struct cf_setting *set);
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static int smist_type(device_t dev, int *type);
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static device_method_t smist_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, smist_identify),
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DEVMETHOD(device_probe, smist_probe),
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DEVMETHOD(device_attach, smist_attach),
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DEVMETHOD(device_detach, smist_detach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, smist_set),
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DEVMETHOD(cpufreq_drv_get, smist_get),
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DEVMETHOD(cpufreq_drv_type, smist_type),
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DEVMETHOD(cpufreq_drv_settings, smist_settings),
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{0, 0}
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};
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static driver_t smist_driver = {
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"smist", smist_methods, sizeof(struct smist_softc)
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};
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static devclass_t smist_devclass;
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DRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0);
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struct piix4_pci_device {
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uint16_t vendor;
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uint16_t device;
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char *desc;
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};
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static struct piix4_pci_device piix4_pci_devices[] = {
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{0x8086, 0x7113, "Intel PIIX4 ISA bridge"},
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{0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"},
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{0, 0, NULL},
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};
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#define SET_OWNERSHIP 0
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#define GET_STATE 1
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#define SET_STATE 2
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static int
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int15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags)
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{
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struct vm86frame vmf;
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bzero(&vmf, sizeof(vmf));
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vmf.vmf_eax = 0x0000E980; /* IST support */
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vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */
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vm86_intcall(0x15, &vmf);
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if (vmf.vmf_eax == 0x47534943) {
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*sig = vmf.vmf_eax;
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*smi_cmd = vmf.vmf_ebx & 0xff;
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*command = (vmf.vmf_ebx >> 16) & 0xff;
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*smi_data = vmf.vmf_ecx;
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*flags = vmf.vmf_edx;
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} else {
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*sig = -1;
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*smi_cmd = -1;
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*command = -1;
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*smi_data = -1;
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*flags = -1;
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}
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return (0);
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}
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static int
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set_ownership(device_t dev)
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{
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int result;
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struct smist_softc *sc;
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vm_paddr_t pmagic;
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static char magic[] = "Copyright (c) 1999 Intel Corporation";
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sc = device_get_softc(dev);
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if (!sc)
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return (ENXIO);
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pmagic = vtophys(magic);
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__asm __volatile(
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"movl $-1, %%edi\n\t"
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"out %%al, (%%dx)\n"
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: "=D" (result)
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: "a" (sc->command),
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"b" (0),
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"c" (0),
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"d" (sc->smi_cmd),
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"S" (pmagic)
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);
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DPRINT(dev, "taking ownership over BIOS return %d\n", result);
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return (result ? ENXIO : 0);
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}
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static int
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getset_state(struct smist_softc *sc, int *state, int function)
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{
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int new_state;
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int result;
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int eax;
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if (!sc)
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return (ENXIO);
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if (function != GET_STATE && function != SET_STATE)
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return (EINVAL);
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DPRINT(sc->dev, "calling GSI\n");
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__asm __volatile(
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"movl $-1, %%edi\n\t"
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"out %%al, (%%dx)\n"
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: "=a" (eax),
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"=b" (new_state),
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"=D" (result)
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: "a" (sc->command),
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"b" (function),
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"c" (*state),
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"d" (sc->smi_cmd)
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);
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DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n",
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eax, new_state, result);
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*state = new_state & 1;
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switch (function) {
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case GET_STATE:
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if (eax)
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return (ENXIO);
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break;
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case SET_STATE:
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if (result)
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return (ENXIO);
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break;
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}
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return (0);
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}
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static void
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smist_identify(driver_t *driver, device_t parent)
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{
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struct piix4_pci_device *id;
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device_t piix4 = NULL;
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if (resource_disabled("ichst", 0))
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return;
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/* Check for a supported processor */
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if (strcmp(cpu_vendor, "GenuineIntel") != 0)
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return;
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switch (cpu_id & 0xff0) {
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case 0x680: /* Pentium III [coppermine] */
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case 0x6a0: /* Pentium III [Tualatin] */
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break;
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default:
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return;
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}
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/* Check for a supported PCI-ISA bridge */
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for (id = piix4_pci_devices; id->desc != NULL; ++id) {
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if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL)
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break;
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}
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if (!piix4)
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return;
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if (bootverbose)
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printf("smist: found supported isa bridge %s\n", id->desc);
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if (device_find_child(parent, "smist", -1) != NULL)
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return;
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if (BUS_ADD_CHILD(parent, 0, "smist", -1) == NULL)
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device_printf(parent, "smist: add child failed\n");
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}
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static int
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smist_probe(device_t dev)
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{
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struct smist_softc *sc;
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device_t ichss_dev, perf_dev;
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int sig, smi_cmd, command, smi_data, flags;
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int type;
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int rv;
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if (resource_disabled("smist", 0))
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return (ENXIO);
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sc = device_get_softc(dev);
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/*
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* If the ACPI perf or ICH SpeedStep drivers have attached and not
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* just offering info, let them manage things.
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*/
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perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
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if (perf_dev && device_is_attached(perf_dev)) {
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rv = CPUFREQ_DRV_TYPE(perf_dev, &type);
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if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
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return (ENXIO);
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}
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ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1);
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if (ichss_dev && device_is_attached(ichss_dev))
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return (ENXIO);
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int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags);
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if (bootverbose)
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device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x "
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"smi_data %.4x flags %.8x\n",
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sig, smi_cmd, command, smi_data, flags);
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if (sig != -1) {
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sc->smi_cmd = smi_cmd;
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sc->smi_data = smi_data;
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/*
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* Sometimes int 15h 'GSIC' returns 0x80 for command, when
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* it is actually 0x82. The Windows driver will overwrite
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* this value given by the registry.
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*/
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if (command == 0x80) {
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device_printf(dev,
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"GSIC returned cmd 0x80, should be 0x82\n");
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command = 0x82;
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}
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sc->command = (sig & 0xffffff00) | (command & 0xff);
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sc->flags = flags;
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} else {
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/* Give some default values */
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sc->smi_cmd = 0xb2;
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sc->smi_data = 0xb3;
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sc->command = 0x47534982;
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sc->flags = 0;
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}
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device_set_desc(dev, "SpeedStep SMI");
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return (-1500);
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}
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static int
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smist_attach(device_t dev)
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{
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struct smist_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* If we can't take ownership over BIOS, then bail out */
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if (set_ownership(dev) != 0)
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return (ENXIO);
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/* Setup some defaults for our exported settings. */
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sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
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sc->sets[0].lat = 1000;
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sc->sets[0].dev = dev;
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sc->sets[1] = sc->sets[0];
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cpufreq_register(dev);
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return (0);
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}
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static int
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smist_detach(device_t dev)
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{
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cpufreq_unregister(dev);
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return (0);
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}
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static int
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smist_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct smist_softc *sc;
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struct cf_setting set;
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int first, i;
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < 2) {
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*count = 2;
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return (E2BIG);
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}
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sc = device_get_softc(dev);
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/*
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* Estimate frequencies for both levels, temporarily switching to
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* the other one if we haven't calibrated it yet.
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*/
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for (i = 0; i < 2; i++) {
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if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
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first = (i == 0) ? 1 : 0;
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smist_set(dev, &sc->sets[i]);
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smist_get(dev, &set);
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smist_set(dev, &sc->sets[first]);
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}
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}
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bcopy(sc->sets, sets, sizeof(sc->sets));
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*count = 2;
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return (0);
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}
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static int
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smist_set(device_t dev, const struct cf_setting *set)
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{
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struct smist_softc *sc;
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int rv, state, req_state, try;
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/* Look up appropriate bit value based on frequency. */
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sc = device_get_softc(dev);
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if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
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req_state = 0;
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else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
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req_state = 1;
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else
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return (EINVAL);
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DPRINT(dev, "requested setting %d\n", req_state);
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rv = getset_state(sc, &state, GET_STATE);
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if (state == req_state)
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return (0);
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try = 3;
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do {
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rv = getset_state(sc, &req_state, SET_STATE);
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/* Sleep for 200 microseconds. This value is just a guess. */
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if (rv)
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DELAY(200);
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} while (rv && --try);
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DPRINT(dev, "set_state return %d, tried %d times\n",
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rv, 4 - try);
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return (rv);
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}
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static int
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smist_get(device_t dev, struct cf_setting *set)
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{
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struct smist_softc *sc;
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uint64_t rate;
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int state;
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int rv;
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sc = device_get_softc(dev);
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rv = getset_state(sc, &state, GET_STATE);
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if (rv != 0)
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return (rv);
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/* If we haven't changed settings yet, estimate the current value. */
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if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
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cpu_est_clockrate(0, &rate);
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sc->sets[state].freq = rate / 1000000;
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DPRINT(dev, "get calibrated new rate of %d\n",
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sc->sets[state].freq);
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}
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*set = sc->sets[state];
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return (0);
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}
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static int
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smist_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_ABSOLUTE;
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return (0);
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}
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@ -16,4 +16,8 @@ SRCS+= acpi_if.h opt_acpi.h
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SRCS+= est.c p4tcc.c powernow.c
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.endif
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.if ${MACHINE} == "i386"
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SRCS+= smist.c
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.endif
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.include <bsd.kmod.mk>
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Block a user