Merge commit bc4bc5aa0 from llvm git (by Justin Hibbits):
Add 8548 CPU definition and attributes 8548 CPU is GCC's name for the e500v2, so accept this in clang. The e500v2 doesn't support lwsync, so define __NO_LWSYNC__ for this as well, as GCC does. Differential Revision: https://reviews.llvm.org/D67787 Merge commit ff0311c4b from llvm git (by Justin Hibbits): [PowerPC]: Add powerpcspe target triple subarch component Summary: This allows the use of '-target powerpcspe-unknown-linux-gnu' or 'powerpcspe-unknown-freebsd' to be used, instead of '-target powerpc-unknown-linux-gnu -mspe'. Reviewed By: dim Differential Revision: https://reviews.llvm.org/D72014 Merge commit ba91dffaf from llvm git (by Fangrui Song): [Driver][PowerPC] Move powerpcspe logic from cc1 to Driver Follow-up of D72014. It is more appropriate to use a target feature instead of a SubTypeArch to express the difference. Reviewed By: #powerpc, jhibbits Differential Revision: https://reviews.llvm.org/D72433 commit 36eedfcb3 from llvm git (by Justin Hibbits): [PowerPC] Fix powerpcspe subtarget enablement in llvm backend Summary: As currently written, -target powerpcspe will enable SPE regardless of disabling the feature later on in the command line. Instead, change this to just set a default CPU to 'e500' instead of a generic CPU. As part of this, add FeatureSPE to the e500 definition. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D72673 These are needed to unbreak the build for powerpcspe. Requested by: jhibbits MFC after: 1 week
This commit is contained in:
Dimitry Andric
parent
0581ad70b7
commit
f8e1cfad89
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=356929
@ -157,6 +157,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
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Builder.defineMacro("_ARCH_A2Q");
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Builder.defineMacro("_ARCH_QP");
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}
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if (ArchDefs & ArchDefineE500)
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Builder.defineMacro("__NO_LWSYNC__");
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if (getTriple().getVendor() == llvm::Triple::BGQ) {
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Builder.defineMacro("__bg__");
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@ -312,6 +314,11 @@ bool PPCTargetInfo::initFeatureMap(
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.Case("pwr8", true)
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.Default(false);
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Features["spe"] = llvm::StringSwitch<bool>(CPU)
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.Case("8548", true)
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.Case("e500", true)
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.Default(false);
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if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
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return false;
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@ -449,16 +456,16 @@ ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
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}
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static constexpr llvm::StringLiteral ValidCPUNames[] = {
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{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
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{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
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{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
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{"7450"}, {"g4+"}, {"750"}, {"970"}, {"g5"},
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{"a2"}, {"a2q"}, {"e500mc"}, {"e5500"}, {"power3"},
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{"pwr3"}, {"power4"}, {"pwr4"}, {"power5"}, {"pwr5"},
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{"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, {"power6x"},
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{"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"}, {"pwr8"},
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{"power9"}, {"pwr9"}, {"powerpc"}, {"ppc"}, {"powerpc64"},
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{"ppc64"}, {"powerpc64le"}, {"ppc64le"},
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{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
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{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
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{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
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{"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
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{"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"},
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{"e5500"}, {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"},
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{"power5"}, {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
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{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
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{"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"powerpc"},
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{"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"},
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};
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bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
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@ -44,7 +44,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
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ArchDefinePwr8 = 1 << 12,
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ArchDefinePwr9 = 1 << 13,
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ArchDefineA2 = 1 << 14,
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ArchDefineA2q = 1 << 15
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ArchDefineA2q = 1 << 15,
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ArchDefineE500 = 1 << 16
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} ArchDefineTypes;
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@ -85,8 +86,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
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// Note: GCC recognizes the following additional cpus:
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// 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
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// 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
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// titan, rs64.
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// 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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@ -145,6 +145,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
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ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
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ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
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ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("8548", "e500", ArchDefineE500)
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.Default(ArchDefineNone);
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}
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return CPUKnown;
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@ -52,10 +52,12 @@ std::string ppc::getPPCTargetCPU(const ArgList &Args) {
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.Case("7450", "7450")
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.Case("G4+", "g4+")
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.Case("750", "750")
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.Case("8548", "e500")
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.Case("970", "970")
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.Case("G5", "g5")
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.Case("a2", "a2")
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.Case("a2q", "a2q")
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.Case("e500", "e500")
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.Case("e500mc", "e500mc")
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.Case("e5500", "e5500")
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.Case("power3", "pwr3")
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@ -100,6 +102,9 @@ const char *ppc::getPPCAsmModeForCPU(StringRef Name) {
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void ppc::getPPCTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args,
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std::vector<StringRef> &Features) {
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if (Triple.getSubArch() == llvm::Triple::PPCSubArch_spe)
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Features.push_back("+spe");
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handleTargetFeaturesGroup(Args, Features, options::OPT_m_ppc_Features_Group);
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ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args);
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@ -128,7 +128,9 @@ class Triple {
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KalimbaSubArch_v4,
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KalimbaSubArch_v5,
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MipsSubArch_r6
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MipsSubArch_r6,
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PPCSubArch_spe
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};
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enum VendorType {
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UnknownVendor,
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@ -389,7 +389,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
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// FIXME: Do we need to support these?
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.Cases("i786", "i886", "i986", Triple::x86)
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.Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
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.Cases("powerpc", "ppc", "ppc32", Triple::ppc)
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.Cases("powerpc", "powerpcspe", "ppc", "ppc32", Triple::ppc)
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.Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
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.Cases("powerpc64le", "ppc64le", Triple::ppc64le)
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.Case("xscale", Triple::arm)
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@ -563,6 +563,9 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) {
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(SubArchName.endswith("r6el") || SubArchName.endswith("r6")))
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return Triple::MipsSubArch_r6;
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if (SubArchName == "powerpcspe")
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return Triple::PPCSubArch_spe;
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StringRef ARMSubArch = ARM::getCanonicalArchName(SubArchName);
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// For now, this is the small part. Early return.
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@ -378,7 +378,7 @@ def : ProcessorModel<"g5", G5Model,
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def : ProcessorModel<"e500", PPCE500Model,
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[DirectiveE500,
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FeatureICBT, FeatureBookE,
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FeatureISEL, FeatureMFTB]>;
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FeatureISEL, FeatureMFTB, FeatureSPE]>;
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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[DirectiveE500mc,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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@ -126,6 +126,8 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
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// If cross-compiling with -march=ppc64le without -mcpu
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if (TargetTriple.getArch() == Triple::ppc64le)
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CPUName = "ppc64le";
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else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
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CPUName = "e500";
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else
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CPUName = "generic";
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}
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