Revert r298477 ("Clear the DDR memory").
There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of hardware (the bitfile synthesized for 4-level page memory system) and clearing was helpful, but then realized support for 4-level page system is untested/broken in both RocketCore and lowRISC.
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=298578
@ -2,4 +2,3 @@
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RISCV opt_global.h
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VFP opt_global.h
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DDR_CLEAR_SIZE opt_global.h
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@ -126,17 +126,6 @@ _start:
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csrr a0, mhartid
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bnez a0, mpentry
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#if defined(DDR_CLEAR_SIZE)
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/* Clear DDR memory */
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la t0, _end
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li t1, DDR_CLEAR_SIZE
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1:
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sd zero, 0(t0)
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addi t0, t0, 8
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bltu t0, t1, 1b
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/* End */
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#endif
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/* Build event queue for current core */
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build_ring
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