Revert r298477 ("Clear the DDR memory").

There is no need to clear all the DDR memory (we only need to clear
BSS section).
I was playing with non-default version of hardware (the bitfile
synthesized for 4-level page memory system) and clearing was helpful,
but then realized support for 4-level page system is untested/broken
in both RocketCore and lowRISC.

sys/conf/options.riscv

@@ -2,4 +2,3 @@
 
 RISCV				opt_global.h
 VFP				opt_global.h
-DDR_CLEAR_SIZE			opt_global.h

sys/riscv/riscv/locore.S

@@ -126,17 +126,6 @@ _start:
 	csrr	a0, mhartid
 	bnez	a0, mpentry
 
-#if defined(DDR_CLEAR_SIZE)
-	/* Clear DDR memory */
-	la	t0, _end
-	li	t1, DDR_CLEAR_SIZE
-1:
-	sd	zero, 0(t0)
-	addi	t0, t0, 8
-	bltu	t0, t1, 1b
-	/* End */
-#endif
-
 	/* Build event queue for current core */
 	build_ring