arm64: allwinner: a64: Add PLL_MIPI
PLL_MIPI is the last important PLL that we missed. Add support for it. Since it's one of the possible parent for TCON0 also add this clock now that we can. While here add some info about what video related clocks should be enabled at boot and with what frequency.
This commit is contained in:
Emmanuel Vadot
parent
0432618600
commit
f99055394d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=352848
@ -311,6 +311,8 @@ aw_ccung_attach(device_t dev)
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case AW_CLK_FRAC:
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aw_clk_frac_register(sc->clkdom, sc->clks[i].clk.frac);
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break;
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case AW_CLK_MIPI:
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aw_clk_mipi_register(sc->clkdom, sc->clks[i].clk.mipi);
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}
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}
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@ -32,6 +32,7 @@
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#include <arm/allwinner/clkng/aw_clk.h>
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#include <arm/allwinner/clkng/aw_clk_m.h>
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#include <arm/allwinner/clkng/aw_clk_mipi.h>
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#include <arm/allwinner/clkng/aw_clk_nkmp.h>
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#include <arm/allwinner/clkng/aw_clk_nm.h>
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#include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
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@ -50,6 +51,7 @@ enum aw_ccung_clk_type {
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AW_CLK_PREDIV_MUX,
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AW_CLK_FRAC,
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AW_CLK_M,
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AW_CLK_MIPI,
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};
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struct aw_ccung_clk {
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@ -63,6 +65,7 @@ struct aw_ccung_clk {
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struct aw_clk_prediv_mux_def *prediv_mux;
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struct aw_clk_frac_def *frac;
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struct aw_clk_m_def *m;
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struct aw_clk_mipi_def *mipi;
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} clk;
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};
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@ -73,6 +73,8 @@ struct aw_clk_init {
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#define AW_CLK_FACTOR_HAS_COND 0x0004
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#define AW_CLK_FACTOR_FIXED 0x0008
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#define AW_CLK_FACTOR_ZERO_IS_ONE 0x0010
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#define AW_CLK_FACTOR_MIN_VALUE 0x0020
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#define AW_CLK_FACTOR_MAX_VALUE 0x0040
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struct aw_clk_factor {
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uint32_t shift; /* Shift bits for the factor */
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@ -85,6 +87,9 @@ struct aw_clk_factor {
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uint32_t cond_width;
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uint32_t cond_value;
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uint32_t min_value;
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uint32_t max_value;
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uint32_t flags; /* Flags */
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};
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@ -147,6 +152,8 @@ aw_clk_factor_get_min(struct aw_clk_factor *factor)
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min = factor->value;
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else if (factor->flags & AW_CLK_FACTOR_ZERO_BASED)
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min = 0;
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else if (factor->flags & AW_CLK_FACTOR_MIN_VALUE)
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min = factor->min_value;
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else
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min = 1;
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@ -166,7 +173,9 @@ aw_clk_factor_get_value(struct aw_clk_factor *factor, uint32_t raw)
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else if (factor->flags & AW_CLK_FACTOR_POWER_OF_TWO) {
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for (val = 0; raw != 1; val++)
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raw >>= 1;
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} else
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} else if (factor->flags & AW_CLK_FACTOR_MAX_VALUE)
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val = factor->max_value;
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else
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val = raw - 1;
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return (val);
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@ -457,6 +466,32 @@ aw_clk_factor_get_value(struct aw_clk_factor *factor, uint32_t raw)
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.prediv.cond_value = _prediv_cond_value, \
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}
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#define MIPI_CLK(_clkname, _id, _name, _pnames, \
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_offset, \
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_kshift, _kwidth, _kflags, _kmin, \
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_mshift, _mwidth, \
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_nshift, _nwidth, \
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_gate_shift, _lock_shift) \
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static struct aw_clk_mipi_def _clkname = { \
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.clkdef = { \
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.id = _id, \
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.name = _name, \
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.parent_names = _pnames, \
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.parent_cnt = nitems(_pnames) \
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}, \
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.offset = _offset, \
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.k.shift = _kshift, \
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.k.width = _kwidth, \
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.k.flags = _kflags, \
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.k.min_value = _kmin, \
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.m.shift = _mshift, \
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.m.width = _mwidth, \
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.n.shift = _nshift, \
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.n.width = _nwidth, \
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.gate_shift = _gate_shift, \
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.lock_shift = _lock_shift, \
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}
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#define MUX_CLK(_clkname, _id, _name, _pnames, \
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_offset, _shift, _width) \
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static struct clk_mux_def _clkname = { \
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300
sys/arm/allwinner/clkng/aw_clk_mipi.c
Normal file
300
sys/arm/allwinner/clkng/aw_clk_mipi.c
Normal file
@ -0,0 +1,300 @@
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/*-
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* Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <arm/allwinner/clkng/aw_clk.h>
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#include <arm/allwinner/clkng/aw_clk_mipi.h>
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#include "clkdev_if.h"
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/* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */
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#define dprintf(format, arg...)
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/*
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* clknode for PLL_MIPI :
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*
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* clk = (pll_video0 * n * k) / m when vfb_sel=0
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* clk depend on sint_frac, sdiv2, s6p25_7p5, pll_feedback_div when vfb_sel=1
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*
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*/
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struct aw_clk_mipi_sc {
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uint32_t offset;
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struct aw_clk_factor k;
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struct aw_clk_factor m;
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struct aw_clk_factor n;
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uint64_t min_freq;
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uint64_t max_freq;
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uint32_t gate_shift;
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uint32_t lock_shift;
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uint32_t lock_retries;
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uint32_t flags;
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};
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#define WRITE4(_clk, off, val) \
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CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
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#define READ4(_clk, off, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), off, val)
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#define DEVICE_LOCK(_clk) \
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CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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#define LDO1_EN_SHIFT 23
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#define LDO2_EN_SHIFT 22
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#define VFB_SEL_SHIFT 16
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static int
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aw_clk_mipi_init(struct clknode *clk, device_t dev)
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{
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struct aw_clk_mipi_sc *sc;
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sc = clknode_get_softc(clk);
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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aw_clk_mipi_set_gate(struct clknode *clk, bool enable)
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{
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struct aw_clk_mipi_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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dprintf("%sabling gate\n", enable ? "En" : "Dis");
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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if (enable) {
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val |= (1 << sc->gate_shift);
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val |= (1 << LDO1_EN_SHIFT);
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val |= (1 << LDO2_EN_SHIFT);
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} else {
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val &= ~(1 << sc->gate_shift);
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val &= ~(1 << LDO1_EN_SHIFT);
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val &= ~(1 << LDO2_EN_SHIFT);
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}
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WRITE4(clk, sc->offset, val);
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DEVICE_UNLOCK(clk);
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return (0);
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}
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static uint64_t
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aw_clk_mipi_find_best(struct aw_clk_mipi_sc *sc, uint64_t fparent, uint64_t *fout,
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uint32_t *factor_k, uint32_t *factor_m, uint32_t *factor_n)
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{
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uint64_t cur, best;
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uint32_t n, k, m;
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best = 0;
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*factor_n = 0;
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*factor_k = 0;
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*factor_m = 0;
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for (n = aw_clk_factor_get_min(&sc->n); n <= aw_clk_factor_get_max(&sc->n); ) {
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for (k = aw_clk_factor_get_min(&sc->k); k <= aw_clk_factor_get_max(&sc->k); ) {
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for (m = aw_clk_factor_get_min(&sc->m); m <= aw_clk_factor_get_max(&sc->m); ) {
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cur = (fparent * n * k) / m;
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if ((*fout - cur) < (*fout - best)) {
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best = cur;
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*factor_n = n;
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*factor_k = k;
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*factor_m = m;
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}
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if (best == *fout)
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return (best);
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m++;
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}
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k++;
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}
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n++;
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}
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return best;
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}
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static int
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aw_clk_mipi_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
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int flags, int *stop)
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{
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struct aw_clk_mipi_sc *sc;
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uint64_t best = 0;
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uint32_t best_k, best_m, best_n;
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uint32_t k, m, n;
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uint32_t val;
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uint32_t retry;
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sc = clknode_get_softc(clk);
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best = aw_clk_mipi_find_best(sc, fparent, fout, &best_k, &best_m, &best_n);
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if (best < sc->min_freq ||
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best > sc->max_freq) {
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printf("%s: Cannot set %ju for %s (min=%ju max=%ju)\n",
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__func__, best, clknode_get_name(clk),
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sc->min_freq, sc->max_freq);
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return (ERANGE);
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}
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if ((flags & CLK_SET_DRYRUN) != 0) {
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*fout = best;
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*stop = 1;
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return (0);
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}
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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/* Disable clock during freq changes */
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val &= ~(1 << sc->gate_shift);
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WRITE4(clk, sc->offset, val);
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k = aw_clk_factor_get_value(&sc->k, best_k);
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n = aw_clk_factor_get_value(&sc->n, best_n);
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m = aw_clk_factor_get_value(&sc->m, best_m);
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val &= ~sc->k.mask;
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val &= ~sc->m.mask;
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val &= ~sc->n.mask;
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val |= k << sc->k.shift;
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val |= m << sc->m.shift;
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val |= n << sc->n.shift;
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/* Write the clock changes */
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WRITE4(clk, sc->offset, val);
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/* Enable clock now that we've change it */
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val |= 1 << sc->gate_shift;
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WRITE4(clk, sc->offset, val);
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DEVICE_UNLOCK(clk);
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for (retry = 0; retry < sc->lock_retries; retry++) {
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READ4(clk, sc->offset, &val);
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if ((val & (1 << sc->lock_shift)) != 0)
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break;
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DELAY(1000);
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}
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*fout = best;
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*stop = 1;
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return (0);
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}
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static int
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aw_clk_mipi_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct aw_clk_mipi_sc *sc;
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uint32_t val, m, n, k;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->offset, &val);
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DEVICE_UNLOCK(clk);
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k = aw_clk_get_factor(val, &sc->k);
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m = aw_clk_get_factor(val, &sc->m);
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n = aw_clk_get_factor(val, &sc->n);
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*freq = (*freq * n * k) / m;
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return (0);
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}
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static clknode_method_t aw_mipi_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, aw_clk_mipi_init),
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CLKNODEMETHOD(clknode_set_gate, aw_clk_mipi_set_gate),
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CLKNODEMETHOD(clknode_recalc_freq, aw_clk_mipi_recalc),
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CLKNODEMETHOD(clknode_set_freq, aw_clk_mipi_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(aw_mipi_clknode, aw_mipi_clknode_class, aw_mipi_clknode_methods,
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sizeof(struct aw_clk_mipi_sc), clknode_class);
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int
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aw_clk_mipi_register(struct clkdom *clkdom, struct aw_clk_mipi_def *clkdef)
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{
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struct clknode *clk;
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struct aw_clk_mipi_sc *sc;
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clk = clknode_create(clkdom, &aw_mipi_clknode_class, &clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->offset = clkdef->offset;
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sc->k.shift = clkdef->k.shift;
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sc->k.width = clkdef->k.width;
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sc->k.mask = ((1 << sc->k.width) - 1) << sc->k.shift;
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sc->k.value = clkdef->k.value;
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sc->k.flags = clkdef->k.flags;
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sc->k.min_value = clkdef->k.min_value;
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sc->m.shift = clkdef->m.shift;
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sc->m.width = clkdef->m.width;
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sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
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sc->m.value = clkdef->m.value;
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sc->m.flags = clkdef->m.flags;
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sc->m.min_value = clkdef->m.min_value;
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sc->n.shift = clkdef->n.shift;
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sc->n.width = clkdef->n.width;
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sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
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sc->n.value = clkdef->n.value;
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sc->n.flags = clkdef->n.flags;
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sc->n.min_value = clkdef->n.min_value;
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sc->min_freq = clkdef->min_freq;
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sc->max_freq = clkdef->max_freq;
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sc->gate_shift = clkdef->gate_shift;
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sc->lock_shift = clkdef->lock_shift;
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sc->lock_retries = clkdef->lock_retries;
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sc->flags = clkdef->flags;
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clknode_register(clkdom, clk);
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return (0);
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}
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53
sys/arm/allwinner/clkng/aw_clk_mipi.h
Normal file
53
sys/arm/allwinner/clkng/aw_clk_mipi.h
Normal file
@ -0,0 +1,53 @@
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/*-
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* Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
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* $FreeBSD$
|
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*/
|
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|
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#ifndef __AW_CLK_MIPI_H__
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#define __AW_CLK_MIPI_H__
|
||||
|
||||
#include <dev/extres/clk/clk.h>
|
||||
|
||||
struct aw_clk_mipi_def {
|
||||
struct clknode_init_def clkdef;
|
||||
uint32_t offset;
|
||||
|
||||
struct aw_clk_factor k;
|
||||
struct aw_clk_factor m;
|
||||
struct aw_clk_factor n;
|
||||
|
||||
uint64_t min_freq;
|
||||
uint64_t max_freq;
|
||||
|
||||
uint32_t gate_shift;
|
||||
uint32_t lock_shift;
|
||||
uint32_t lock_retries;
|
||||
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
int aw_clk_mipi_register(struct clkdom *clkdom, struct aw_clk_mipi_def *clkdef);
|
||||
|
||||
#endif /* __AW_CLK_MIPI_H__ */
|
||||
@ -70,6 +70,7 @@ __FBSDID("$FreeBSD$");
|
||||
#define CLK_PLL_PERIPH1_2X 14
|
||||
#define CLK_PLL_VIDEO1 15
|
||||
#define CLK_PLL_GPU 16
|
||||
#define CLK_PLL_MIPI 17
|
||||
#define CLK_PLL_HSIC 18
|
||||
#define CLK_PLL_DE 19
|
||||
#define CLK_PLL_DDR1 20
|
||||
@ -397,7 +398,15 @@ FRAC_CLK(pll_gpu_clk,
|
||||
24, 25, /* mode sel, freq sel */
|
||||
192000000, 600000000); /* min freq, max freq */
|
||||
|
||||
/* PLL MIPI is missing */
|
||||
static const char *pll_mipi_parents[] = {"pll_video0"};
|
||||
MIPI_CLK(pll_mipi_clk,
|
||||
CLK_PLL_MIPI,
|
||||
"pll_mipi", pll_mipi_parents,
|
||||
0x40,
|
||||
4, 2, AW_CLK_FACTOR_MIN_VALUE, 2,
|
||||
0, 3,
|
||||
8, 4,
|
||||
31, 28);
|
||||
|
||||
static const char *pll_hsic_parents[] = {"osc24M"};
|
||||
FRAC_CLK(pll_hsic_clk,
|
||||
@ -642,8 +651,13 @@ M_CLK(de_clk,
|
||||
31, /* gate */
|
||||
AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
|
||||
|
||||
/* TCON0/1 Needs mux table */
|
||||
static const char *tcon1_parents[] = {"pll_video0", "pll_video0", "pll_video1"};
|
||||
static const char *tcon0_parents[] = {"pll_mipi", NULL, "pll_video0-2x"};
|
||||
MUX_CLK(tcon0_clk,
|
||||
CLK_TCON0, /* id */
|
||||
"tcon0", tcon0_parents, /* name, parents */
|
||||
0x118, 24, 2); /* offset, shift, width */
|
||||
|
||||
static const char *tcon1_parents[] = {"pll_video0", NULL, "pll_video1"};
|
||||
M_CLK(tcon1_clk,
|
||||
CLK_TCON1, "tcon1", tcon1_parents, /* id, name, parents */
|
||||
0x11C, /* offset */
|
||||
@ -726,7 +740,7 @@ static struct aw_ccung_clk a64_ccu_clks[] = {
|
||||
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk},
|
||||
{ .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
|
||||
{ .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
|
||||
/* PLL_MIPI */
|
||||
{ .type = AW_CLK_MIPI, .clk.mipi = &pll_mipi_clk},
|
||||
{ .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk},
|
||||
{ .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
|
||||
{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk},
|
||||
@ -757,6 +771,7 @@ static struct aw_ccung_clk a64_ccu_clks[] = {
|
||||
{ .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk},
|
||||
{ .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk},
|
||||
{ .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk},
|
||||
{ .type = AW_CLK_MUX, .clk.mux = &tcon0_clk},
|
||||
{ .type = AW_CLK_DIV, .clk.div = &axi_clk},
|
||||
{ .type = AW_CLK_DIV, .clk.div = &apb1_clk},
|
||||
{ .type = AW_CLK_DIV, .clk.div = &apb_clk},
|
||||
@ -774,6 +789,10 @@ static struct aw_clk_init a64_init_clks[] = {
|
||||
{"ahb1", "pll_periph0", 0, false},
|
||||
{"ahb2", "pll_periph0", 0, false},
|
||||
{"dram", "pll_ddr0", 0, false},
|
||||
{"pll_de", NULL, 432000000, true},
|
||||
{"de", "pll_de", 0, true},
|
||||
{"tcon0", "pll_video0-2x", 0, false},
|
||||
{"tcon1", "pll_video1", 0, false},
|
||||
};
|
||||
|
||||
static int
|
||||
|
||||
@ -51,6 +51,7 @@ arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt
|
||||
arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt
|
||||
arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt
|
||||
|
||||
Loading…
Reference in New Issue
Block a user