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Use stxa_sync() when accessing the LSU control register to avoid undefined

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behaviour.
This commit is contained in:
Thomas Moestl 2002-02-13 16:25:33 +00:00
parent fd2ee897e4
commit fac409f6bf
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=90621
1 changed files with 6 additions and 6 deletions
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12
sys/sparc64/sparc64/db_hwwatch.c
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@ -53,11 +53,11 @@ watch_phys_set_mask(vm_offset_t pa, u_long mask)
{
u_long lsucr;
stxa(AA_DMMU_PWPR, ASI_DMMU, pa & (((2UL << 38) - 1) << 3));
stxa_sync(AA_DMMU_PWPR, ASI_DMMU, pa & (((2UL << 38) - 1) << 3));
lsucr = ldxa(0, ASI_LSU_CTL_REG);
lsucr = ((lsucr | LSU_PW) & ~LSU_PM_MASK) |
(mask << LSU_PM_SHIFT);
stxa(0, ASI_LSU_CTL_REG, lsucr);
stxa_sync(0, ASI_LSU_CTL_REG, lsucr);
return (0);
}
@ -92,7 +92,7 @@ watch_phys_get(int *bm)
void
watch_phys_clear()
{
stxa(0, ASI_LSU_CTL_REG,
stxa_sync(0, ASI_LSU_CTL_REG,
ldxa(0, ASI_LSU_CTL_REG) & ~LSU_PW);
}
@ -108,11 +108,11 @@ watch_virt_set_mask(vm_offset_t va, u_long mask)
{
u_long lsucr;
stxa(AA_DMMU_VWPR, ASI_DMMU, va & (((2UL << 41) - 1) << 3));
stxa_sync(AA_DMMU_VWPR, ASI_DMMU, va & (((2UL << 41) - 1) << 3));
lsucr = ldxa(0, ASI_LSU_CTL_REG);
lsucr = ((lsucr | LSU_VW) & ~LSU_VM_MASK) |
(mask << LSU_VM_SHIFT);
stxa(0, ASI_LSU_CTL_REG, lsucr);
stxa_sync(0, ASI_LSU_CTL_REG, lsucr);
return (0);
}
@ -147,7 +147,7 @@ watch_virt_get(int *bm)
void
watch_virt_clear()
{
stxa(0, ASI_LSU_CTL_REG,
stxa_sync(0, ASI_LSU_CTL_REG,
ldxa(0, ASI_LSU_CTL_REG) & ~LSU_VW);
}