Enable proper configuration of CESA MBUS windows
For all Marvell devices, MBUS windows configuration is done in a common place. Only CESA was an exception, so move its related code from driver to mv_common.c. This way it uses same proper DRAM information, same as all other interfaces instead of parsing DT /memory node directly. Submitted by: Marcin Wojtas <mw@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: loos Differential revision: https://reviews.freebsd.org/D10723
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0a6542a309
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=318522
@ -76,6 +76,7 @@ MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
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static int win_eth_can_remap(int i);
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static int decode_win_cesa_valid(void);
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static int decode_win_cpu_valid(void);
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static int decode_win_usb_valid(void);
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static int decode_win_usb3_valid(void);
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@ -91,6 +92,7 @@ static void decode_win_cpu_setup(void);
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#ifdef SOC_MV_ARMADAXP
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static int decode_win_sdram_fixup(void);
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#endif
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static void decode_win_cesa_setup(u_long);
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static void decode_win_usb_setup(u_long);
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static void decode_win_usb3_setup(u_long);
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static void decode_win_eth_setup(u_long);
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@ -101,6 +103,7 @@ static void decode_win_sdhci_setup(u_long);
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static void decode_win_idma_setup(u_long);
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static void decode_win_xor_setup(u_long);
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static void decode_win_cesa_dump(u_long);
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static void decode_win_usb_dump(u_long);
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static void decode_win_usb3_dump(u_long);
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static void decode_win_eth_dump(u_long base);
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@ -146,6 +149,7 @@ static struct soc_node_spec soc_nodes[] = {
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{ "mrvl,sata", &decode_win_sata_setup, NULL },
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{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
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{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
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{ "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump },
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{ "mrvl,pcie", &decode_win_pcie_setup, NULL },
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{ NULL, NULL, NULL },
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};
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@ -574,7 +578,7 @@ soc_decode_win(void)
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!decode_win_eth_valid() || !decode_win_idma_valid() ||
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!decode_win_pcie_valid() || !decode_win_sata_valid() ||
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!decode_win_xor_valid() || !decode_win_usb3_valid() ||
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!decode_win_sdhci_valid())
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!decode_win_sdhci_valid() || !decode_win_cesa_valid())
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return (EINVAL);
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decode_win_cpu_setup();
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@ -601,6 +605,11 @@ WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
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WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)
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WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)
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WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)
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WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)
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WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
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WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
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WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
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@ -1070,6 +1079,63 @@ ddr_target(int i)
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return (0);
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}
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/**************************************************************************
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* CESA windows routines
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**************************************************************************/
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static int
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decode_win_cesa_valid(void)
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{
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return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
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}
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static void
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decode_win_cesa_dump(u_long base)
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{
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int i;
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for (i = 0; i < MV_WIN_CESA_MAX; i++)
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printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
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win_cesa_cr_read(base, i), win_cesa_br_read(base, i));
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}
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/*
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* Set CESA decode windows.
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*/
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static void
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decode_win_cesa_setup(u_long base)
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{
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uint32_t br, cr;
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int i, j;
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for (i = 0; i < MV_WIN_CESA_MAX; i++) {
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win_cesa_cr_write(base, i, 0);
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win_cesa_br_write(base, i, 0);
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}
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/* Only access to active DRAM banks is required */
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for (i = 0; i < MV_WIN_DDR_MAX; i++) {
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if (ddr_is_active(i)) {
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br = ddr_base(i);
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cr = (((ddr_size(i) - 1) & 0xffff0000) |
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(ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
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(ddr_target(i) << IO_WIN_TGT_SHIFT) |
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IO_WIN_ENA_MASK);
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/* Set the first free CESA window */
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for (j = 0; j < MV_WIN_CESA_MAX; j++) {
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if (win_cesa_cr_read(base, j) & 0x1)
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continue;
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win_cesa_br_write(base, j, br);
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win_cesa_cr_write(base, j, cr);
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break;
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}
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}
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}
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}
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/**************************************************************************
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* USB windows routines
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**************************************************************************/
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@ -216,6 +216,11 @@
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#define MV_WIN_CESA_ATTR(eng_sel) 0
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#endif
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/* CESA TDMA address decoding registers */
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
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#define MV_WIN_CESA_MAX 4
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#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
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#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
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#define MV_WIN_USB_MAX 4
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@ -69,7 +69,6 @@ __FBSDID("$FreeBSD$");
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#include "cryptodev_if.h"
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvwin.h>
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#include <arm/mv/mvvar.h>
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#include "cesa.h"
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@ -80,7 +79,6 @@ static void cesa_intr(void *);
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static int cesa_newsession(device_t, u_int32_t *, struct cryptoini *);
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static int cesa_freesession(device_t, u_int64_t);
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static int cesa_process(device_t, struct cryptop *, int);
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static int decode_win_cesa_setup(struct cesa_softc *sc);
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static struct resource_spec cesa_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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@ -1085,13 +1083,6 @@ cesa_attach(device_t dev)
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goto err0;
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}
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/* Setup CESA decoding windows */
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error = decode_win_cesa_setup(sc);
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if (error) {
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device_printf(dev, "could not setup decoding windows\n");
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goto err1;
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}
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/* Acquire SRAM base address */
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error = cesa_setup_sram(sc);
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if (error) {
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@ -1706,50 +1697,3 @@ cesa_process(device_t dev, struct cryptop *crp, int hint)
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return (0);
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}
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/*
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* Set CESA TDMA decode windows.
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*/
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static int
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decode_win_cesa_setup(struct cesa_softc *sc)
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{
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struct mem_region availmem_regions[FDT_MEM_REGIONS];
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int availmem_regions_sz;
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uint32_t br, cr, i;
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/* Grab physical memory regions information from DTS */
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if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz,
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NULL) != 0)
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return (ENXIO);
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if (availmem_regions_sz > MV_WIN_CESA_MAX) {
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device_printf(sc->sc_dev, "Too much memory regions, cannot "
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" set CESA windows to cover whole DRAM \n");
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return (ENXIO);
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}
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/* Disable and clear all CESA windows */
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for (i = 0; i < MV_WIN_CESA_MAX; i++) {
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CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), 0);
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CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0);
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}
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/* Fill CESA TDMA decoding windows with information acquired from DTS */
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for (i = 0; i < availmem_regions_sz; i++) {
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br = availmem_regions[i].mr_start;
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cr = availmem_regions[i].mr_size;
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/* Don't add entries with size lower than 64KB */
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if (cr & 0xffff0000) {
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cr = (((cr - 1) & 0xffff0000) |
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(MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) |
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(MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) |
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MV_WIN_CPU_ENABLE_BIT);
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CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), br);
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CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr);
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}
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}
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return (0);
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}
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@ -350,11 +350,6 @@ struct cesa_chain_info {
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#define CESA_TDMA_EMR_BOTH_HIT CESA_TDMA_ECR_BOTH_HIT
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#define CESA_TDMA_EMR_DATA_ERROR CESA_TDMA_ECR_DATA_ERROR
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/* CESA TDMA address decoding registers */
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
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#define MV_WIN_CESA_MAX 4
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/* CESA SA registers definitions */
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#define CESA_SA_CMD 0x0E00
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#define CESA_SA_CMD_ACTVATE (1 << 0)
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