Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.
Sponsored by: DARPA, AFRL
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=347351
@ -5,10 +5,13 @@ cddl/dev/dtrace/riscv/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}"
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cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
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crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support
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crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb
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dev/cadence/if_cgem.c optional cgem
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dev/ofw/ofw_cpu.c optional fdt
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dev/uart/uart_cpu_fdt.c optional uart fdt
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dev/uart/uart_dev_lowrisc.c optional uart_lowrisc
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dev/xilinx/axi_quad_spi.c optional xilinx_spi
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dev/xilinx/axidma.c optional axidma xdma
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dev/xilinx/if_xae.c optional xae
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kern/kern_clocksource.c standard
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kern/msi_if.m standard
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kern/pic_if.m standard
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@ -102,6 +102,16 @@ device uart # Generic UART driver
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device uart_lowrisc # lowRISC UART driver
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device uart_ns8250 # ns8250-type UART driver
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# Ethernet drivers
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device miibus # MII bus support
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device cgem # Cadence Gigabit Ethernet MAC
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device xae # Xilinx AXI Ethernet MAC
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# DMA support
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device xdma # DMA interface
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device axidma # Xilinx AXI DMA Controller
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# Uncomment for memory disk
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# options MD_ROOT
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# options MD_ROOT_SIZE=32768 # 32MB ram disk
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