Add memory barriers (fence instructions) so the data wrotten by hardware
to physical address now can be read by VA. This fixes operation on Rocket Core (FPGA). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
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parent
6c1838e37e
commit
fd3dc9f439
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=298476
@ -115,6 +115,7 @@ htif_blk_intr(void *arg, uint64_t entry)
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data = HTIF_DEV_DATA(entry);
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if (sc->curtag == data) {
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wmb();
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sc->cmd_done = 1;
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wakeup(&sc->intr_chan);
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} else {
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@ -198,6 +199,7 @@ htif_blk_task(void *arg)
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{
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struct htif_blk_request req __aligned(HTIF_ALIGN);
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struct htif_blk_softc *sc;
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uint64_t req_paddr;
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struct bio *bp;
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uint64_t paddr;
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uint64_t cmd;
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@ -217,11 +219,13 @@ htif_blk_task(void *arg)
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if (bp->bio_cmd == BIO_READ || bp->bio_cmd == BIO_WRITE) {
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HTIF_BLK_LOCK(sc);
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rmb();
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req.offset = (bp->bio_pblkno * sc->disk->d_sectorsize);
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req.size = bp->bio_bcount;
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paddr = vtophys(bp->bio_data);
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KASSERT(paddr != 0, ("paddr is 0"));
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req.addr = paddr;
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sc->curtag++;
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req.tag = sc->curtag;
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cmd = sc->index;
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@ -230,9 +234,9 @@ htif_blk_task(void *arg)
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cmd |= (HTIF_CMD_READ << HTIF_CMD_SHIFT);
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else
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cmd |= (HTIF_CMD_WRITE << HTIF_CMD_SHIFT);
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paddr = vtophys(&req);
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KASSERT(paddr != 0, ("paddr is 0"));
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cmd |= paddr;
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req_paddr = vtophys(&req);
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KASSERT(req_paddr != 0, ("req_paddr is 0"));
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cmd |= req_paddr;
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sc->cmd_done = 0;
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htif_command(cmd);
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