hwpmc: Add basic Intel Alderlake CPUs support.
The PMC subsystem is not designed for non-uniform CPU capabilities (P/E-cores are different), but at least several working architectural events like cpu_clk_unhalted.thread_p should be better than nothing. MFC after: 1 month
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@ -781,6 +781,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
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case PMC_CPU_INTEL_SKYLAKE_XEON:
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case PMC_CPU_INTEL_ICELAKE:
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case PMC_CPU_INTEL_ICELAKE_XEON:
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case PMC_CPU_INTEL_ALDERLAKE:
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default:
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break;
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}
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@ -163,6 +163,27 @@ pmc_intel_initialize(void)
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cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
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nclasses = 3;
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break;
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case 0x3D:
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case 0x47:
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cputype = PMC_CPU_INTEL_BROADWELL;
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nclasses = 3;
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break;
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case 0x4f:
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case 0x56:
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cputype = PMC_CPU_INTEL_BROADWELL_XEON;
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nclasses = 3;
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break;
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case 0x3C: /* Per Intel document 325462-045US 01/2013. */
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case 0x45: /* Per Intel document 325462-045US 09/2014. */
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cputype = PMC_CPU_INTEL_HASWELL;
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nclasses = 3;
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break;
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case 0x3F: /* Per Intel document 325462-045US 09/2014. */
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case 0x46: /* Per Intel document 325462-045US 09/2014. */
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/* Should 46 be XEON. probably its own? */
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cputype = PMC_CPU_INTEL_HASWELL_XEON;
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nclasses = 3;
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break;
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/* Skylake */
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case 0x4e:
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case 0x5e:
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@ -195,25 +216,9 @@ pmc_intel_initialize(void)
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cputype = PMC_CPU_INTEL_ICELAKE_XEON;
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nclasses = 3;
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break;
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case 0x3D:
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case 0x47:
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cputype = PMC_CPU_INTEL_BROADWELL;
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nclasses = 3;
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break;
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case 0x4f:
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case 0x56:
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cputype = PMC_CPU_INTEL_BROADWELL_XEON;
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nclasses = 3;
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break;
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case 0x3F: /* Per Intel document 325462-045US 09/2014. */
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case 0x46: /* Per Intel document 325462-045US 09/2014. */
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/* Should 46 be XEON. probably its own? */
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cputype = PMC_CPU_INTEL_HASWELL_XEON;
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nclasses = 3;
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break;
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case 0x3C: /* Per Intel document 325462-045US 01/2013. */
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case 0x45: /* Per Intel document 325462-045US 09/2014. */
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cputype = PMC_CPU_INTEL_HASWELL;
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case 0x97:
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case 0x9A:
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cputype = PMC_CPU_INTEL_ALDERLAKE;
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nclasses = 3;
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break;
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case 0x37:
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@ -250,40 +255,9 @@ pmc_intel_initialize(void)
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error = pmc_tsc_initialize(pmc_mdep, ncpus);
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if (error)
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goto error;
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switch (cputype) {
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/*
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* Intel Core, Core 2 and Atom processors.
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*/
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_ATOM_GOLDMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_BROADWELL_XEON:
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case PMC_CPU_INTEL_SKYLAKE_XEON:
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case PMC_CPU_INTEL_SKYLAKE:
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case PMC_CPU_INTEL_ICELAKE:
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case PMC_CPU_INTEL_ICELAKE_XEON:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_NEHALEM_EX:
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case PMC_CPU_INTEL_IVYBRIDGE:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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case PMC_CPU_INTEL_WESTMERE_EX:
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case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE_XEON:
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_HASWELL_XEON:
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MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF);
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error = pmc_core_initialize(pmc_mdep, ncpus, verov);
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break;
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default:
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KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
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}
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MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF);
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error = pmc_core_initialize(pmc_mdep, ncpus, verov);
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if (error) {
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pmc_tsc_finalize(pmc_mdep);
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goto error;
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@ -338,34 +312,7 @@ pmc_intel_finalize(struct pmc_mdep *md)
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{
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pmc_tsc_finalize(md);
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switch (md->pmd_cputype) {
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_ATOM_SILVERMONT:
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case PMC_CPU_INTEL_ATOM_GOLDMONT:
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case PMC_CPU_INTEL_BROADWELL:
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case PMC_CPU_INTEL_BROADWELL_XEON:
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case PMC_CPU_INTEL_SKYLAKE_XEON:
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case PMC_CPU_INTEL_SKYLAKE:
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case PMC_CPU_INTEL_ICELAKE:
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case PMC_CPU_INTEL_ICELAKE_XEON:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_NEHALEM_EX:
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case PMC_CPU_INTEL_HASWELL:
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case PMC_CPU_INTEL_HASWELL_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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case PMC_CPU_INTEL_WESTMERE_EX:
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case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
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case PMC_CPU_INTEL_IVYBRIDGE_XEON:
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pmc_core_finalize(md);
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break;
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default:
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KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
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}
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pmc_core_finalize(md);
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/*
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* Uncore.
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@ -113,6 +113,7 @@ extern char pmc_cpuid[PMC_CPUID_LEN];
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__PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \
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__PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \
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__PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \
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__PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \
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__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
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__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
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__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
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