Rework the interrupt code and add support for interrupt filtering
(INTR_FILTER). This includes: o Save a pointer to the sapic structure and IRQ for every vector, so that we can quickly EOI, mask and unmask the interrupt. o Add locking to the sapic code now that we can reprogram a sapic on multiple CPUs at the same time. o Use u_int for the vector and IRQ. We only have 256 vectors, so using a 64-bit type for it is rather excessive. o Properly handle concurrent registration of a handler for the same vector. Since vectors have a corresponding priority, we should not map IRQs to vectors in a linear fashion, but rather pick a vector that has a priority in line with the interrupt type. This is left for later. The vector/IRQ interchange has been untangled as much as possible to make this easier. Approved by: re (blacket)
This commit is contained in:
Marcel Moolenaar
parent
8a2a70cb02
commit
fe1c66b9d7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=171664
@ -49,6 +49,7 @@
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <sys/syslog.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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@ -76,7 +77,7 @@ struct evcnt clock_intr_evcnt; /* event counter for clock intrs. */
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extern int mp_ipi_test;
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#endif
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volatile int mc_expected, mc_received;
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static void ia64_dispatch_intr(void *, u_int);
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static void
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dummy_perf(unsigned long vector, struct trapframe *tf)
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@ -127,7 +128,7 @@ SYSCTL_INT(_debug_clock, OID_AUTO, adjust_ticks, CTLFLAG_RD,
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&adjust_ticks, 0, "Total number of ITC interrupts with adjustment");
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int
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interrupt(u_int64_t vector, struct trapframe *tf)
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interrupt(u_int vector, struct trapframe *tf)
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{
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struct thread *td;
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volatile struct ia64_interrupt_block *ib = IA64_INTERRUPT_BLOCK;
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@ -146,7 +147,7 @@ interrupt(u_int64_t vector, struct trapframe *tf)
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*/
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if (vector == 0) {
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vector = ib->ib_inta;
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printf("ExtINT interrupt: vector=%ld\n", vector);
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printf("ExtINT interrupt: vector=%u\n", vector);
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if (vector == 15)
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goto stray;
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}
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@ -251,93 +252,115 @@ interrupt(u_int64_t vector, struct trapframe *tf)
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#define IA64_HARDWARE_IRQ_BASE 0x20
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struct ia64_intr {
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struct intr_event *event; /* interrupt event */
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volatile long *cntp; /* interrupt counter */
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struct intr_event *event; /* interrupt event */
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volatile long *cntp; /* interrupt counter */
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struct sapic *sapic;
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u_int irq;
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};
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static struct mtx ia64_intrs_lock;
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static struct ia64_intr *ia64_intrs[256];
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extern struct sapic *ia64_sapics[];
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extern int ia64_sapic_count;
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static void
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ithds_init(void *dummy)
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ia64_intr_eoi(void *arg)
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{
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u_int vector = (uintptr_t)arg;
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struct ia64_intr *i;
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mtx_init(&ia64_intrs_lock, "intr table", NULL, MTX_SPIN);
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i = ia64_intrs[vector];
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if (i != NULL)
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sapic_eoi(i->sapic, vector);
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}
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SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
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#ifdef INTR_FILTER
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static void
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ia64_send_eoi(uintptr_t vector)
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ia64_intr_disable(void *arg)
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{
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int irq, i;
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u_int vector = (uintptr_t)arg;
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struct ia64_intr *i;
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irq = vector - IA64_HARDWARE_IRQ_BASE;
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for (i = 0; i < ia64_sapic_count; i++) {
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struct sapic *sa = ia64_sapics[i];
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if (irq >= sa->sa_base && irq <= sa->sa_limit)
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sapic_eoi(sa, vector);
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i = ia64_intrs[vector];
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if (i != NULL) {
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sapic_eoi(i->sapic, vector);
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sapic_mask(i->sapic, i->irq);
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}
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}
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static void
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ia64_intr_enable(void *arg)
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{
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u_int vector = (uintptr_t)arg;
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struct ia64_intr *i;
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i = ia64_intrs[vector];
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if (i != NULL)
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sapic_unmask(i->sapic, i->irq);
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}
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#endif
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int
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ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags,
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void **cookiep, volatile long *cntp)
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ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
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{
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struct ia64_intr *i;
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int errcode;
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intptr_t vector = irq + IA64_HARDWARE_IRQ_BASE;
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struct sapic *sa;
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char *intrname;
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u_int vector;
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int error;
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/* Get the I/O SAPIC that corresponds to the IRQ. */
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sa = sapic_lookup(irq);
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if (sa == NULL)
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return (EINVAL);
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/*
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* XXX - Can we have more than one device on a vector? If so, we have
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* a race condition here that needs to be worked around similar to
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* the fashion done in the i386 inthand_add() function.
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* XXX - There's a priority implied by the choice of vector.
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* We should therefore relate the vector to the interrupt type.
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*/
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/* First, check for an existing hash table entry for this vector. */
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mtx_lock_spin(&ia64_intrs_lock);
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i = ia64_intrs[vector];
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mtx_unlock_spin(&ia64_intrs_lock);
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vector = irq + IA64_HARDWARE_IRQ_BASE;
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i = ia64_intrs[vector];
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if (i == NULL) {
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/* None was found, so create an entry. */
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i = malloc(sizeof(struct ia64_intr), M_DEVBUF, M_NOWAIT);
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if (i == NULL)
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return ENOMEM;
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if (cntp == NULL)
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i->cntp = intrcnt + irq + INTRCNT_ISA_IRQ;
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else
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i->cntp = cntp;
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if (name != NULL && *name != '\0') {
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/* XXX needs abstraction. Too error phrone. */
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intrname = intrnames + (irq + INTRCNT_ISA_IRQ) *
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INTRNAME_LEN;
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memset(intrname, ' ', INTRNAME_LEN - 1);
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bcopy(name, intrname, strlen(name));
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}
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errcode = intr_event_create(&i->event, (void *)vector, 0,
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(void (*)(void *))ia64_send_eoi, "intr:");
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if (errcode) {
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return (ENOMEM);
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#ifdef INTR_FILTER
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error = intr_event_create(&i->event, (void *)(uintptr_t)vector,
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0, ia64_intr_enable, ia64_intr_eoi, ia64_intr_disable,
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"irq%u:", irq);
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#else
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error = intr_event_create(&i->event, (void *)(uintptr_t)vector,
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0, ia64_intr_eoi, "irq%u:", irq);
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#endif
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if (error) {
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free(i, M_DEVBUF);
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return errcode;
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return (error);
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}
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mtx_lock_spin(&ia64_intrs_lock);
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ia64_intrs[vector] = i;
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mtx_unlock_spin(&ia64_intrs_lock);
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if (!atomic_cmpset_ptr(&ia64_intrs[vector], NULL, i)) {
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intr_event_destroy(i->event);
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free(i, M_DEVBUF);
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i = ia64_intrs[vector];
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} else {
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i->sapic = sa;
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i->irq = irq;
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i->cntp = intrcnt + irq + INTRCNT_ISA_IRQ;
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if (name != NULL && *name != '\0') {
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/* XXX needs abstraction. Too error prone. */
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intrname = intrnames +
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(irq + INTRCNT_ISA_IRQ) * INTRNAME_LEN;
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memset(intrname, ' ', INTRNAME_LEN - 1);
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bcopy(name, intrname, strlen(name));
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}
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sapic_enable(i->sapic, irq, vector);
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}
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}
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/* Second, add this handler. */
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errcode = intr_event_add_handler(i->event, name, filter, handler, arg,
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error = intr_event_add_handler(i->event, name, filter, handler, arg,
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intr_priority(flags), flags, cookiep);
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if (errcode)
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return errcode;
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return (sapic_enable(irq, vector));
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return (error);
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}
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int
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@ -347,27 +370,33 @@ ia64_teardown_intr(void *cookie)
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return (intr_event_remove_handler(cookie));
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}
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void
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ia64_dispatch_intr(void *frame, unsigned long vector)
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static void
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ia64_dispatch_intr(void *frame, u_int vector)
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{
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struct ia64_intr *i;
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struct intr_event *ie; /* our interrupt event */
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#ifndef INTR_FILTER
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struct intr_handler *ih;
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int error, thread, ret;
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#endif
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/*
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* Find the interrupt thread for this vector.
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*/
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i = ia64_intrs[vector];
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if (i == NULL)
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return; /* no event for this vector */
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KASSERT(i != NULL, ("%s: unassigned vector", __func__));
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if (i->cntp)
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atomic_add_long(i->cntp, 1);
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(*i->cntp)++;
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ie = i->event;
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KASSERT(ie != NULL, ("interrupt vector without an event"));
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KASSERT(ie != NULL, ("%s: interrupt without event", __func__));
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#ifdef INTR_FILTER
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if (intr_event_handle(ie, frame) != 0) {
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ia64_intr_disable((void *)(uintptr_t)vector);
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log(LOG_ERR, "stray irq%u\n", i->irq);
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}
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#else
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/*
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* As an optimization, if an event has no handlers, don't
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* schedule it to run.
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@ -403,37 +432,41 @@ ia64_dispatch_intr(void *frame, unsigned long vector)
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if (thread) {
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error = intr_event_schedule_thread(ie);
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KASSERT(error == 0, ("got an impossible stray interrupt"));
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KASSERT(error == 0, ("%s: impossible stray", __func__));
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} else
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ia64_send_eoi(vector);
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ia64_intr_eoi((void *)(uintptr_t)vector);
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#endif
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}
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#ifdef DDB
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static void
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db_show_vector(int vector)
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db_print_vector(u_int vector, int always)
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{
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int irq, i;
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struct ia64_intr *i;
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irq = vector - IA64_HARDWARE_IRQ_BASE;
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for (i = 0; i < ia64_sapic_count; i++) {
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struct sapic *sa = ia64_sapics[i];
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if (irq >= sa->sa_base && irq <= sa->sa_limit)
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sapic_print(sa, irq - sa->sa_base);
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}
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i = ia64_intrs[vector];
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if (i != NULL) {
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db_printf("vector %u (%p): ", vector, i);
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sapic_print(i->sapic, i->irq);
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} else if (always)
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db_printf("vector %u: unassigned\n", vector);
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}
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DB_SHOW_COMMAND(irq, db_show_irq)
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DB_SHOW_COMMAND(vector, db_show_vector)
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{
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int vector;
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u_int vector;
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if (have_addr) {
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vector = ((addr >> 4) % 16) * 10 + (addr % 16);
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db_show_vector(vector);
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if (vector >= 256)
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db_printf("error: vector %u not in range [0..255]\n",
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vector);
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else
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db_print_vector(vector, 1);
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} else {
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for (vector = IA64_HARDWARE_IRQ_BASE;
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vector < IA64_HARDWARE_IRQ_BASE + 64; vector++)
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db_show_vector(vector);
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for (vector = 0; vector < 256; vector++)
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db_print_vector(vector, 0);
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}
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}
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@ -447,7 +447,7 @@ nexus_setup_intr(device_t bus, device_t child, struct resource *irq,
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return (error);
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error = ia64_setup_intr(device_get_nameunit(child),
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rman_get_start(irq), filter, ihand, arg, flags, cookiep, 0);
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rman_get_start(irq), filter, ihand, arg, flags, cookiep);
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return (error);
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}
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@ -33,6 +33,8 @@
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <machine/intr.h>
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@ -67,7 +69,22 @@ struct sapic_rte {
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u_int64_t rte_destination_id :8;
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};
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static u_int32_t
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struct sapic *
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sapic_lookup(u_int irq)
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{
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struct sapic *sa;
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int i;
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for (i = 0; i < ia64_sapic_count; i++) {
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sa = ia64_sapics[i];
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if (irq >= sa->sa_base && irq <= sa->sa_limit)
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return (sa);
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}
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return (NULL);
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}
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static __inline u_int32_t
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sapic_read(struct sapic *sa, int which)
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{
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vm_offset_t reg = sa->sa_registers;
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@ -77,7 +94,7 @@ sapic_read(struct sapic *sa, int which)
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return *(volatile u_int32_t *) (reg + SAPIC_IO_WINDOW);
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}
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static void
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static __inline void
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sapic_write(struct sapic *sa, int which, u_int32_t value)
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{
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vm_offset_t reg = sa->sa_registers;
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@ -88,77 +105,70 @@ sapic_write(struct sapic *sa, int which, u_int32_t value)
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ia64_mf();
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}
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static void
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static __inline void
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sapic_read_rte(struct sapic *sa, int which, struct sapic_rte *rte)
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{
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u_int32_t *p = (u_int32_t *) rte;
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register_t c;
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c = intr_disable();
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p[0] = sapic_read(sa, SAPIC_RTE_BASE + 2*which);
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p[1] = sapic_read(sa, SAPIC_RTE_BASE + 2*which + 1);
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intr_restore(c);
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p[0] = sapic_read(sa, SAPIC_RTE_BASE + 2 * which);
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p[1] = sapic_read(sa, SAPIC_RTE_BASE + 2 * which + 1);
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}
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static void
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static __inline void
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sapic_write_rte(struct sapic *sa, int which, struct sapic_rte *rte)
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{
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u_int32_t *p = (u_int32_t *) rte;
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register_t c;
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c = intr_disable();
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sapic_write(sa, SAPIC_RTE_BASE + 2*which, p[0]);
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sapic_write(sa, SAPIC_RTE_BASE + 2*which + 1, p[1]);
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intr_restore(c);
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sapic_write(sa, SAPIC_RTE_BASE + 2 *which, p[0]);
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sapic_write(sa, SAPIC_RTE_BASE + 2 *which + 1, p[1]);
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}
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int
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sapic_config_intr(int irq, enum intr_trigger trig, enum intr_polarity pol)
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sapic_config_intr(u_int irq, enum intr_trigger trig, enum intr_polarity pol)
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{
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struct sapic_rte rte;
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struct sapic *sa;
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int i;
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for (i = 0; i < ia64_sapic_count; i++) {
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sa = ia64_sapics[i];
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if (irq < sa->sa_base || irq > sa->sa_limit)
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continue;
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sa = sapic_lookup(irq);
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if (sa == NULL)
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return (EINVAL);
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sapic_read_rte(sa, irq - sa->sa_base, &rte);
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if (trig != INTR_TRIGGER_CONFORM)
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rte.rte_trigger_mode = (trig == INTR_TRIGGER_EDGE) ?
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SAPIC_TRIGGER_EDGE : SAPIC_TRIGGER_LEVEL;
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else
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rte.rte_trigger_mode = (irq < 16) ?
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SAPIC_TRIGGER_EDGE : SAPIC_TRIGGER_LEVEL;
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if (pol != INTR_POLARITY_CONFORM)
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rte.rte_polarity = (pol == INTR_POLARITY_HIGH) ?
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SAPIC_POLARITY_HIGH : SAPIC_POLARITY_LOW;
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else
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rte.rte_polarity = (irq < 16) ? SAPIC_POLARITY_HIGH :
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SAPIC_POLARITY_LOW;
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sapic_write_rte(sa, irq - sa->sa_base, &rte);
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return (0);
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}
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|
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return (ENOENT);
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mtx_lock_spin(&sa->sa_mtx);
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sapic_read_rte(sa, irq - sa->sa_base, &rte);
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if (trig != INTR_TRIGGER_CONFORM)
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rte.rte_trigger_mode = (trig == INTR_TRIGGER_EDGE) ?
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SAPIC_TRIGGER_EDGE : SAPIC_TRIGGER_LEVEL;
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else
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rte.rte_trigger_mode = (irq < 16) ? SAPIC_TRIGGER_EDGE :
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SAPIC_TRIGGER_LEVEL;
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if (pol != INTR_POLARITY_CONFORM)
|
||||
rte.rte_polarity = (pol == INTR_POLARITY_HIGH) ?
|
||||
SAPIC_POLARITY_HIGH : SAPIC_POLARITY_LOW;
|
||||
else
|
||||
rte.rte_polarity = (irq < 16) ? SAPIC_POLARITY_HIGH :
|
||||
SAPIC_POLARITY_LOW;
|
||||
sapic_write_rte(sa, irq - sa->sa_base, &rte);
|
||||
mtx_unlock_spin(&sa->sa_mtx);
|
||||
return (0);
|
||||
}
|
||||
|
||||
struct sapic *
|
||||
sapic_create(int id, int base, u_int64_t address)
|
||||
sapic_create(u_int id, u_int base, u_int64_t address)
|
||||
{
|
||||
struct sapic_rte rte;
|
||||
struct sapic *sa;
|
||||
int i, max;
|
||||
u_int i, max;
|
||||
|
||||
sa = malloc(sizeof(struct sapic), M_SAPIC, M_NOWAIT);
|
||||
if (!sa)
|
||||
return 0;
|
||||
sa = malloc(sizeof(struct sapic), M_SAPIC, M_ZERO | M_NOWAIT);
|
||||
if (sa == NULL)
|
||||
return (NULL);
|
||||
|
||||
sa->sa_id = id;
|
||||
sa->sa_base = base;
|
||||
sa->sa_registers = IA64_PHYS_TO_RR6(address);
|
||||
|
||||
mtx_init(&sa->sa_mtx, "I/O SAPIC lock", NULL, MTX_SPIN);
|
||||
|
||||
max = (sapic_read(sa, SAPIC_VERSION) >> 16) & 0xff;
|
||||
sa->sa_limit = base + max;
|
||||
|
||||
@ -183,39 +193,58 @@ sapic_create(int id, int base, u_int64_t address)
|
||||
}
|
||||
|
||||
int
|
||||
sapic_enable(int irq, int vector)
|
||||
sapic_enable(struct sapic *sa, u_int irq, u_int vector)
|
||||
{
|
||||
struct sapic_rte rte;
|
||||
struct sapic *sa;
|
||||
uint64_t lid = ia64_get_lid();
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ia64_sapic_count; i++) {
|
||||
sa = ia64_sapics[i];
|
||||
if (irq < sa->sa_base || irq > sa->sa_limit)
|
||||
continue;
|
||||
|
||||
sapic_read_rte(sa, irq - sa->sa_base, &rte);
|
||||
rte.rte_destination_id = (lid >> 24) & 255;
|
||||
rte.rte_destination_eid = (lid >> 16) & 255;
|
||||
rte.rte_delivery_mode = SAPIC_DELMODE_LOWPRI;
|
||||
rte.rte_vector = vector;
|
||||
rte.rte_mask = 0;
|
||||
sapic_write_rte(sa, irq - sa->sa_base, &rte);
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
mtx_lock_spin(&sa->sa_mtx);
|
||||
sapic_read_rte(sa, irq - sa->sa_base, &rte);
|
||||
rte.rte_destination_id = (lid >> 24) & 255;
|
||||
rte.rte_destination_eid = (lid >> 16) & 255;
|
||||
rte.rte_delivery_mode = SAPIC_DELMODE_LOWPRI;
|
||||
rte.rte_vector = vector;
|
||||
rte.rte_mask = 0;
|
||||
sapic_write_rte(sa, irq - sa->sa_base, &rte);
|
||||
mtx_unlock_spin(&sa->sa_mtx);
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
sapic_eoi(struct sapic *sa, int vector)
|
||||
sapic_eoi(struct sapic *sa, u_int vector)
|
||||
{
|
||||
vm_offset_t reg = sa->sa_registers;
|
||||
|
||||
*(volatile u_int32_t *) (reg + SAPIC_APIC_EOI) = vector;
|
||||
*(volatile u_int32_t *)(reg + SAPIC_APIC_EOI) = vector;
|
||||
ia64_mf();
|
||||
}
|
||||
|
||||
/* Expected to be called with interrupts disabled. */
|
||||
void
|
||||
sapic_mask(struct sapic *sa, u_int irq)
|
||||
{
|
||||
struct sapic_rte rte;
|
||||
|
||||
mtx_lock_spin(&sa->sa_mtx);
|
||||
sapic_read_rte(sa, irq - sa->sa_base, &rte);
|
||||
rte.rte_mask = 1;
|
||||
sapic_write_rte(sa, irq - sa->sa_base, &rte);
|
||||
mtx_unlock_spin(&sa->sa_mtx);
|
||||
}
|
||||
|
||||
/* Expected to be called with interrupts disabled. */
|
||||
void
|
||||
sapic_unmask(struct sapic *sa, u_int irq)
|
||||
{
|
||||
struct sapic_rte rte;
|
||||
|
||||
mtx_lock_spin(&sa->sa_mtx);
|
||||
sapic_read_rte(sa, irq - sa->sa_base, &rte);
|
||||
rte.rte_mask = 0;
|
||||
sapic_write_rte(sa, irq - sa->sa_base, &rte);
|
||||
mtx_unlock_spin(&sa->sa_mtx);
|
||||
}
|
||||
|
||||
static int
|
||||
sysctl_machdep_apic(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
@ -233,8 +262,10 @@ sysctl_machdep_apic(SYSCTL_HANDLER_ARGS)
|
||||
sa = ia64_sapics[apic];
|
||||
count = sa->sa_limit - sa->sa_base + 1;
|
||||
for (index = 0; index < count; index++) {
|
||||
mtx_lock_spin(&sa->sa_mtx);
|
||||
sapic_read_rte(sa, index, &rte);
|
||||
if (rte.rte_mask != 0)
|
||||
mtx_unlock_spin(&sa->sa_mtx);
|
||||
if (rte.rte_vector == 0)
|
||||
continue;
|
||||
len = sprintf(buf,
|
||||
" 0x%02x %3d: (%02x,%02x): %3d %d %d %s %s %s %s %s\n",
|
||||
@ -261,24 +292,22 @@ sysctl_machdep_apic(SYSCTL_HANDLER_ARGS)
|
||||
#include <ddb/ddb.h>
|
||||
|
||||
void
|
||||
sapic_print(struct sapic *sa, int input)
|
||||
sapic_print(struct sapic *sa, u_int irq)
|
||||
{
|
||||
struct sapic_rte rte;
|
||||
|
||||
sapic_read_rte(sa, input, &rte);
|
||||
if (rte.rte_mask == 0) {
|
||||
db_printf("%3d %d %d %s %s %s %s %s ID=%x EID=%x\n",
|
||||
rte.rte_vector,
|
||||
rte.rte_delivery_mode,
|
||||
rte.rte_destination_mode,
|
||||
rte.rte_delivery_status ? "DS" : " ",
|
||||
rte.rte_polarity ? "low-active " : "high-active",
|
||||
rte.rte_rirr ? "RIRR" : " ",
|
||||
rte.rte_trigger_mode ? "level" : "edge ",
|
||||
rte.rte_flushen ? "F" : " ",
|
||||
rte.rte_destination_id,
|
||||
rte.rte_destination_eid);
|
||||
}
|
||||
db_printf("sapic=%u, irq=%u: ", sa->sa_id, irq);
|
||||
sapic_read_rte(sa, irq - sa->sa_base, &rte);
|
||||
db_printf("%3d %x->%x:%x %d %s %s %s %s %s %s\n", rte.rte_vector,
|
||||
rte.rte_delivery_mode,
|
||||
rte.rte_destination_id, rte.rte_destination_eid,
|
||||
rte.rte_destination_mode,
|
||||
rte.rte_delivery_status ? "DS" : " ",
|
||||
rte.rte_polarity ? "low-active " : "high-active",
|
||||
rte.rte_rirr ? "RIRR" : " ",
|
||||
rte.rte_trigger_mode ? "level" : "edge ",
|
||||
rte.rte_flushen ? "F" : " ",
|
||||
rte.rte_mask ? "(masked)" : "");
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -48,13 +48,8 @@ extern u_int64_t ia64_lapic_address;
|
||||
#define IA64_INTERRUPT_BLOCK \
|
||||
(struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address)
|
||||
|
||||
struct sapic;
|
||||
|
||||
void ia64_add_sapic(struct sapic *sa);
|
||||
int ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
|
||||
driver_intr_t handler, void *arg, enum intr_type flags,
|
||||
void **cookiep, volatile long *cntp);
|
||||
driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep);
|
||||
int ia64_teardown_intr(void *cookie);
|
||||
void ia64_dispatch_intr(void *frame, unsigned long vector);
|
||||
|
||||
#endif /* !_MACHINE_INTR_H_ */
|
||||
|
||||
@ -84,7 +84,7 @@ int ia64_highfp_drop(struct thread *);
|
||||
int ia64_highfp_save(struct thread *);
|
||||
void ia64_init(void);
|
||||
void ia64_probe_sapics(void);
|
||||
int interrupt(uint64_t, struct trapframe *);
|
||||
int interrupt(u_int, struct trapframe *);
|
||||
void map_gateway_page(void);
|
||||
void map_pal_code(void);
|
||||
void map_vhpt(uintptr_t);
|
||||
|
||||
@ -30,10 +30,11 @@
|
||||
#define _MACHINE_SAPICVAR_H_
|
||||
|
||||
struct sapic {
|
||||
int sa_id; /* I/O SAPIC Id */
|
||||
int sa_base; /* ACPI vector base */
|
||||
int sa_limit; /* last ACPI vector handled here */
|
||||
struct mtx sa_mtx;
|
||||
vm_offset_t sa_registers; /* virtual address of sapic */
|
||||
u_int sa_id; /* I/O SAPIC Id */
|
||||
u_int sa_base; /* ACPI vector base */
|
||||
u_int sa_limit; /* last ACPI vector handled here */
|
||||
};
|
||||
|
||||
#define SAPIC_TRIGGER_EDGE 0
|
||||
@ -49,12 +50,16 @@ struct sapic {
|
||||
#define SAPIC_DELMODE_INIT 5
|
||||
#define SAPIC_DELMODE_EXTINT 7
|
||||
|
||||
int sapic_config_intr(int irq, enum intr_trigger, enum intr_polarity);
|
||||
struct sapic *sapic_create(int id, int base, uint64_t address);
|
||||
int sapic_enable(int irq, int vector);
|
||||
void sapic_eoi(struct sapic *sa, int vector);
|
||||
int sapic_config_intr(u_int irq, enum intr_trigger, enum intr_polarity);
|
||||
struct sapic *sapic_create(u_int id, u_int base, uint64_t address);
|
||||
int sapic_enable(struct sapic *sa, u_int irq, u_int vector);
|
||||
void sapic_eoi(struct sapic *sa, u_int vector);
|
||||
struct sapic *sapic_lookup(u_int irq);
|
||||
void sapic_mask(struct sapic *sa, u_int irq);
|
||||
void sapic_unmask(struct sapic *sa, u_int irq);
|
||||
|
||||
#ifdef DDB
|
||||
void sapic_print(struct sapic *sa, int input);
|
||||
void sapic_print(struct sapic *sa, u_int irq);
|
||||
#endif
|
||||
|
||||
#endif /* ! _MACHINE_SAPICVAR_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user