mlx5: Implement support for configuring PCIe packet write ordering via a sysctl.
Submitted by: hselasky@ Approved by: hselasky (mentor) MFC after: 1 week Sponsored by: Mellanox Technologies
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=341563
@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
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* Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -30,6 +30,11 @@
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#include <dev/mlx5/driver.h>
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#include "mlx5_core.h"
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static int mlx5_relaxed_ordering_write;
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SYSCTL_INT(_hw_mlx5, OID_AUTO, relaxed_ordering_write, CTLFLAG_RWTUN,
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&mlx5_relaxed_ordering_write, 0,
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"Set to enable relaxed ordering for PCIe writes");
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void mlx5_init_mr_table(struct mlx5_core_dev *dev)
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{
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struct mlx5_mr_table *table = &dev->priv.mr_table;
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@ -63,6 +68,14 @@ int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
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mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
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MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
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MLX5_SET(mkc, mkc, mkey_7_0, key);
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if (mlx5_relaxed_ordering_write != 0) {
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if (MLX5_CAP_GEN(dev, relaxed_ordering_write))
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MLX5_SET(mkc, mkc, relaxed_ordering_write, 1);
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else
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return (-EPROTONOSUPPORT);
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}
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if (callback)
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return mlx5_cmd_exec_cb(dev, in, inlen, out, outlen,
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callback, context);
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@ -933,7 +933,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 log_max_cq[0x5];
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u8 log_max_eq_sz[0x8];
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u8 reserved_6[0x2];
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u8 relaxed_ordering_write[1];
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u8 reserved_6[0x1];
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u8 log_max_mkey[0x6];
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u8 reserved_7[0xc];
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u8 log_max_eq[0x4];
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@ -2424,9 +2425,13 @@ enum {
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};
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struct mlx5_ifc_mkc_bits {
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u8 reserved_0[0x1];
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u8 reserved_at_0[0x1];
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u8 free[0x1];
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u8 reserved_1[0xd];
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u8 reserved_at_2[0x1];
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u8 access_mode_4_2[0x3];
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u8 reserved_at_6[0x7];
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u8 relaxed_ordering_write[0x1];
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u8 reserved_at_e[0x1];
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u8 small_fence_on_rdma_read_response[0x1];
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u8 umr_en[0x1];
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u8 a[0x1];
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