Make Marvell mv_pci.c driver generic
PCI ports differ between Marvell SoCs, but have the same compatible in FDT. Identification is made based on parent compatible during attach. For ArmadaXP skipping enable procedure is necessary. To achieve it sc_skip_enable_procedure flag is used. For Armada38x find root procedure is necessary. For other SoCs root link is always at slot 0. sc_enable_find_root_slot flag is used to select proper behaviour. Marvell armv5 platforms does not support msi. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: andrew Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14735
This commit is contained in:
Marcin Wojtas
parent
244af1d4db
commit
fefc2cf777
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=331953
@ -308,6 +308,9 @@ struct mv_pcib_softc {
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int sc_type;
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int sc_mode; /* Endpoint / Root Complex */
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int sc_msi_supported;
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int sc_skip_enable_procedure;
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int sc_enable_find_root_slot;
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struct ofw_bus_iinfo sc_pci_iinfo;
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};
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@ -341,11 +344,10 @@ static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int mv_pcib_route_interrupt(device_t, device_t, int);
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#if defined(SOC_MV_ARMADAXP)
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static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
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static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
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static int mv_pcib_release_msi(device_t, device_t, int, int *);
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#endif
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/*
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* Bus interface definitions.
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@ -371,11 +373,10 @@ static device_method_t mv_pcib_methods[] = {
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DEVMETHOD(pcib_write_config, mv_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
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DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
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#if defined(SOC_MV_ARMADAXP)
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DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
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DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
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#endif
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/* OFW bus interface */
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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@ -442,9 +443,19 @@ mv_pcib_attach(device_t self)
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if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
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sc->sc_type = MV_TYPE_PCIE;
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sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
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if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
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sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
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sc->sc_enable_find_root_slot = 1;
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} else {
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sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
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#if __ARM_ARCH >= 6
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sc->sc_skip_enable_procedure = 1;
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#endif
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}
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} else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
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sc->sc_type = MV_TYPE_PCI;
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sc->sc_win_target = MV_WIN_PCI_TARGET;
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@ -541,9 +552,11 @@ static void
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mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
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{
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uint32_t val;
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#if !defined(SOC_MV_ARMADAXP)
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int timeout;
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if (sc->sc_skip_enable_procedure)
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goto pcib_enable_root_mode;
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/*
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* Check if PCIE device is enabled.
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*/
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@ -561,9 +574,8 @@ mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
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PCIE_REG_STATUS);
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}
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}
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#endif
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pcib_enable_root_mode:
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if (sc->sc_mode == MV_MODE_ROOT) {
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/*
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* Enable PCI bridge.
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@ -1042,20 +1054,19 @@ mv_pcib_maxslots(device_t dev)
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static int
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mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
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{
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#if defined(SOC_MV_ARMADA38X)
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struct mv_pcib_softc *sc = device_get_softc(dev);
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uint32_t vendor, device;
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/* On platforms other than Armada38x, root link is always at slot 0 */
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if (!sc->sc_enable_find_root_slot)
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return (slot == 0);
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vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
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PCIR_VENDOR_LENGTH);
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device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
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PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
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return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
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#else
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/* On platforms other than Armada38x, root link is always at slot 0 */
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return (slot == 0);
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#endif
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}
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static uint32_t
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@ -1159,7 +1170,6 @@ mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
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return (0);
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}
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#if defined(SOC_MV_ARMADAXP)
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static int
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mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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@ -1167,6 +1177,9 @@ mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
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struct mv_pcib_softc *sc;
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sc = device_get_softc(dev);
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if (!sc->sc_msi_supported)
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return (ENOTSUP);
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irq = irq - MSI_IRQ;
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/* validate parameters */
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@ -1175,7 +1188,9 @@ mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
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return (EINVAL);
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}
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#if __ARM_ARCH >= 6
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mv_msi_data(irq, addr, data);
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#endif
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debugf("%s: irq: %d addr: %jx data: %x\n",
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__func__, irq, *addr, *data);
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@ -1190,10 +1205,13 @@ mv_pcib_alloc_msi(device_t dev, device_t child, int count,
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struct mv_pcib_softc *sc;
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u_int start = 0, i;
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sc = device_get_softc(dev);
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if (!sc->sc_msi_supported)
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return (ENOTSUP);
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if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
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return (EINVAL);
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sc = device_get_softc(dev);
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mtx_lock(&sc->sc_msi_mtx);
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for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
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@ -1227,6 +1245,9 @@ mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
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u_int i;
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sc = device_get_softc(dev);
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if(!sc->sc_msi_supported)
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return (ENOTSUP);
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mtx_lock(&sc->sc_msi_mtx);
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for (i = 0; i < count; i++)
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@ -1235,5 +1256,3 @@ mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
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mtx_unlock(&sc->sc_msi_mtx);
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return (0);
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}
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#endif
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@ -64,12 +64,8 @@
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#define MV_PCI_PORTS 1 /* 1x PCIE */
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#elif defined(SOC_MV_DISCOVERY)
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#define MV_PCI_PORTS 8 /* 8x PCIE */
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#elif defined(SOC_MV_ARMADAXP)
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#define MV_PCI_PORTS 3 /* 3x PCIE */
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#elif defined(SOC_MV_ARMADA38X)
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#define MV_PCI_PORTS 4 /* 4x PCIE */
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#else
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#error "MV_PCI_PORTS not configured !"
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#define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */
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#endif
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/* PCI/PCIE Memory */
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@ -77,15 +73,11 @@
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#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */
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#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
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#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
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#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \
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MV_PCI_MEM_SLICE_SIZE))
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/* PCI/PCIE I/O */
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#define MV_PCI_IO_PHYS_BASE 0xBF000000
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#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */
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#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
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#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
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#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE))
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#define MV_PCI_VA_MEM_BASE 0
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#define MV_PCI_VA_IO_BASE 0
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@ -131,22 +123,9 @@
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#define MV_PCI_BASE (MV_BASE + 0x30000)
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#define MV_PCI_SIZE 0x2000
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#if defined(SOC_MV_ARMADA38X)
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#define MV_PCIE_BASE (MV_BASE + 0x80000)
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#else
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#define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)
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#define MV_PCIE_BASE (MV_BASE + 0x40000)
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#endif
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#define MV_PCIE_SIZE 0x2000
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#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000)
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#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000)
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#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000)
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#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000)
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#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000)
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#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000)
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#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000)
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#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000)
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#define MV_SDIO_BASE (MV_BASE + 0x90000)
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#define MV_SDIO_SIZE 0x10000
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@ -255,22 +234,24 @@
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#define MV_XOR_CHAN_MAX 2
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#define MV_XOR_NON_REMAP 4
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#define MV_WIN_PCIE_TARGET_ARMADAXP(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n) (0xE0 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
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#define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
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#define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
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#define MV_WIN_PCIE_IO_ATTR(n) 0xE0
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#elif defined(SOC_MV_ARMADAXP)
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#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
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#elif defined(SOC_MV_ARMADA38X)
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#define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4)
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#define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
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#define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
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#elif defined(SOC_MV_ORION)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
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#define MV_WIN_PCIE_IO_ATTR(n) 0x51
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#else
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#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
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#endif
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#define MV_WIN_PCI_TARGET 3
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