Fix handling of NX pages on capable CPUs. Thanks to kib for prodding me
in the right direction.
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parent
5bc9ca019a
commit
ff30eecffe
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=217341
@ -650,8 +650,7 @@ moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
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moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
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&moea64_pvo_kunmanaged, pa, pa,
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pte_lo, PVO_WIRED | PVO_LARGE |
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VM_PROT_EXECUTE);
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pte_lo, PVO_WIRED | PVO_LARGE);
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}
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}
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PMAP_UNLOCK(kernel_pmap);
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@ -1266,8 +1265,8 @@ moea64_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
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} else
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pte_lo |= LPTE_BR;
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if (prot & VM_PROT_EXECUTE)
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pvo_flags |= VM_PROT_EXECUTE;
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if ((prot & VM_PROT_EXECUTE) == 0)
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pte_lo |= LPTE_NOEXEC;
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if (wired)
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pvo_flags |= PVO_WIRED;
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@ -1692,8 +1691,7 @@ moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
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PMAP_LOCK(kernel_pmap);
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error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
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&moea64_pvo_kunmanaged, va, pa, pte_lo,
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PVO_WIRED | VM_PROT_EXECUTE);
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&moea64_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
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if (error != 0 && error != ENOENT)
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panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
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@ -2191,8 +2189,8 @@ moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
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LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
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if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
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if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
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(pvo->pvo_pte.lpte.pte_lo & LPTE_PP) ==
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(pte_lo & LPTE_PP)) {
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(pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
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== (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
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if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
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/* Re-insert if spilled */
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i = MOEA64_PTE_INSERT(mmu, ptegidx,
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@ -2246,8 +2244,6 @@ moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
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LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
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pvo->pvo_vaddr &= ~ADDR_POFF;
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if (!(flags & VM_PROT_EXECUTE))
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pte_lo |= LPTE_NOEXEC;
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if (flags & PVO_WIRED)
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pvo->pvo_vaddr |= PVO_WIRED;
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if (pvo_head != &moea64_pvo_kunmanaged)
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@ -523,7 +523,9 @@ trap_pfault(struct trapframe *frame, int user)
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p = td->td_proc;
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if (frame->exc == EXC_ISI) {
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eva = frame->srr0;
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ftype = VM_PROT_READ | VM_PROT_EXECUTE;
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ftype = VM_PROT_EXECUTE;
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if (frame->srr1 & SRR1_ISI_PFAULT)
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ftype |= VM_PROT_READ;
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} else {
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eva = frame->cpu.aim.dar;
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if (frame->cpu.aim.dsisr & DSISR_STORE)
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@ -111,6 +111,9 @@
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#define SPR_SDR1 0x019 /* .68 Page table base address register */
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#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
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#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
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#define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */
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#define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */
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#define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */
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#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */
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#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
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#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
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