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Partially revert r208162 while waiting for review on a more comprehensive

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fix. On Apple OpenPICs, the low/high bit of the interrupt sense is only
respected for interrupt 0. We currently erroneously program all OpenPIC
interrupts level high instead of level low by default, which only matters
for some G5 systems where the SATA controllers use IRQ 0.

This change is a quick fix that will be reverted once the effect of
changing the default interrupt sense on embedded systems is known.

MFC after:	3 days
This commit is contained in:
Nathan Whitehorn 2010-06-05 16:25:25 +00:00
parent 36d0d27786
commit ff6f4d01f1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=208836
1 changed files with 7 additions and 0 deletions
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7
sys/dev/ata/chipsets/ata-serverworks.c
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@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$");
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <vm/uma.h>
#ifdef __powerpc__
#include <machine/intr_machdep.h>
#endif
#include <machine/stdarg.h>
#include <machine/resource.h>
#include <machine/bus.h>
@ -217,6 +220,10 @@ ata_serverworks_ch_attach(device_t dev)
ch->hw.tf_write = ata_serverworks_tf_write;
#ifdef __powerpc__
ch->hw.status = ata_serverworks_status;
/* Make sure that our interrupt is edge triggered */
powerpc_config_intr(bus_get_resource_start(device_get_parent(dev),
SYS_RES_IRQ, 0), INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
#endif
if (ctlr->chip->chipid == ATA_K2) {