sfxge(4): support FEC mode settings
Medford2 controllers support control and reporting of FEC modes for 25G and higher links. See SF-109306-TC for suggested usage in client code. Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18197
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commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=341122
@ -61,6 +61,12 @@ mcdi_phy_decode_cap(
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CHECK_CAP(ASYM);
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CHECK_CAP(ASYM);
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CHECK_CAP(AN);
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CHECK_CAP(AN);
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CHECK_CAP(DDM);
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CHECK_CAP(DDM);
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CHECK_CAP(BASER_FEC);
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CHECK_CAP(BASER_FEC_REQUESTED);
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CHECK_CAP(RS_FEC);
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CHECK_CAP(RS_FEC_REQUESTED);
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CHECK_CAP(25G_BASER_FEC);
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CHECK_CAP(25G_BASER_FEC_REQUESTED);
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#undef CHECK_CAP
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#undef CHECK_CAP
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mask = 0;
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mask = 0;
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@ -94,6 +100,22 @@ mcdi_phy_decode_cap(
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
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mask |= (1 << EFX_PHY_CAP_AN);
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mask |= (1 << EFX_PHY_CAP_AN);
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/* FEC caps (supported on Medford2 and later) */
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN))
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mask |= (1 << EFX_PHY_CAP_BASER_FEC);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN))
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mask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN))
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mask |= (1 << EFX_PHY_CAP_RS_FEC);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN))
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mask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN))
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mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC);
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if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN))
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mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
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*maskp = mask;
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*maskp = mask;
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}
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}
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@ -350,6 +372,25 @@ ef10_phy_reconfigure(
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1);
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PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_BASER_FEC_REQUESTED,
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(cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_RS_FEC_REQUESTED,
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(cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_25G_BASER_FEC,
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(cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1);
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MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
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PHY_CAP_25G_BASER_FEC_REQUESTED,
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(cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1);
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#if EFSYS_OPT_LOOPBACK
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#if EFSYS_OPT_LOOPBACK
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
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MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
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epp->ep_loopback_type);
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epp->ep_loopback_type);
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@ -904,6 +904,12 @@ typedef enum efx_phy_cap_type_e {
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EFX_PHY_CAP_100000FDX,
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EFX_PHY_CAP_100000FDX,
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EFX_PHY_CAP_25000FDX,
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EFX_PHY_CAP_25000FDX,
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EFX_PHY_CAP_50000FDX,
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EFX_PHY_CAP_50000FDX,
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EFX_PHY_CAP_BASER_FEC,
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EFX_PHY_CAP_BASER_FEC_REQUESTED,
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EFX_PHY_CAP_RS_FEC,
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EFX_PHY_CAP_RS_FEC_REQUESTED,
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EFX_PHY_CAP_25G_BASER_FEC,
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EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
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EFX_PHY_CAP_NTYPES
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EFX_PHY_CAP_NTYPES
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} efx_phy_cap_type_t;
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} efx_phy_cap_type_t;
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