Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).
Copy the files for the sibyte support (except files in sys/conf and
sys/mips/conf). This targets the Broadcom SWARM board (bcm91250) and
the SB-1 core in the BCM1250 SoC. This work was done by Neel Natu.
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
correctly. The 256MB segment is formed by taking the top 4 bits
of the address of the instruction in the "branch delay" slot
as opposed to the 'J' or 'JAL' instruction itself.
Approved by: imp (mentor)
PAGE_SIZE to (2 * PAGE_SIZE). It depends on the memory allocated by
pmap_steal_memory() being aligned to a PAGE_SIZE boundary.
Approved by: imp (mentor)
This replaces d_mmap() with the d_mmap2() implementation and also
changes the type of offset to vm_ooffset_t.
Purge d_mmap2().
All driver modules will need to be rebuilt since D_VERSION is also
bumped.
Reviewed by: jhb@
MFC after: Not in this lifetime...
here yet, so I've not connected it to the build. I think that we'll
need to move something into the processor specific part of the mips
port by requiring mips_cpu_ptrace or platform_cpu_ptrace be provided
by the ports to get/set processor specific registers, ala SSE
registers on x86.
statement. When no caches support was added, it looks like
TARGET_OCTEON was bogusly moved inside the if. Also, include
opt_cputype.h to make TARGET_OCTEON actually active.
# now we die in pmap init somewhere... Most likely because 32MB of RAM is
# too tight given the load address we're using.
o Introduce a uart bus space so that we don't have to hack dev/uart to do 8
byte reads. This also handles the shift properly, so reset the shift we
want dev/uart doing to 0. In effect, this bus space makes the octeon
registers have an interface to dev/uart that looks just like the old ISA
bus, but does the necessary 64-bit read/write to the bus. We only support
read/write operations. We do all the widths, but likely could get away
with only 64-bit and 8-bit given the restricted nature of use of this bus.
o use bus_space_map to set the .bsh rather than a direct assignment.
o Minor cleanup of uart_cpu_getdev to make it conform more to the other
implementations.
o Add some coments for future work.
# with these changes, we now make it through cninit, but there's still some
# problem that's preventing output, as well as another problem that causes
# us to call panic just after we return from cninit() in platform_start.
