Commit Graph

1059 Commits

Author SHA1 Message Date
Bruce Evans
a67ef0a77a Don't implement anything in the ffs family in <machine/cpufunc.h>
in the non-_KERNEL case.  This "fixes" applications that include
this "kernel-only" header and also include <strings.h> (or get
<strings.h> via the default _BSD_VISIBLE pollution in <string.h>.
In C++ there was a fatal error: the declaration specifies C linkage
but the implementation gives C++ linkage.  In C there was only a
static/extern mismatch if the headers were included in a certain order
order, and a partially redundant declaration for all include orders;
gcc emits incomplete or wrong diagnostics for these, but only for
compiling with -Wsystem-headers and certain other warning options, so
the problem was usually not seen for C.

Ports breakage reported by:	kris
2004-03-11 13:38:54 +00:00
Peter Wemm
4f6c19e593 MFi386: re-sort non-gcc function prototypes, trim includes 2004-03-08 00:24:15 +00:00
Alan Cox
925d2fedf5 Remove unused declarations. (Some time ago, these variables became fields
of vm/vm.h's struct kva_md_info.)
2004-03-07 07:13:15 +00:00
Lukas Ertl
1bcf24ee9d Fix syntax errors and wrong function prototypes in several MD header
files when using non-GNUC compilers.

PR:             kern/58515
Submitted by:   Stefan Farfeleder <stefan@fafoe.narf.at>
Approved by:    grog (mentor), obrien
2004-03-05 09:19:59 +00:00
David E. O'Brien
e81bb67370 AMD64 versions. 2004-03-03 07:00:48 +00:00
Peter Wemm
170a05510d Re-add user_dbreg_trap() for debug register support 2004-01-29 00:05:03 +00:00
Peter Wemm
1c89210c83 We can simplify a lot of things now that we don't have to worry about
hardware bugs on external 386 cpus and now that we can depend on SSE.
2004-01-28 23:55:58 +00:00
Peter Wemm
d957532a87 Add dbreg struct definitions for /proc/*/dbregs and a place to store the
registers in the pcb
2004-01-28 23:54:31 +00:00
Peter Wemm
1182b177ff Re-add debug register functions 2004-01-28 23:53:04 +00:00
Peter Wemm
b29fd7c4db MFi386: mp_topology(). 2004-01-28 23:51:16 +00:00
Peter Wemm
5e465ab919 MFi386: add THERMTRIP msr values 2004-01-28 23:47:22 +00:00
Poul-Henning Kamp
37f0ad870c remove elan_mmcr, I'm not sure I understand what it did here in the
first place.
2004-01-17 13:13:48 +00:00
Jacques Vidrine
e4dc8baa84 Provide sysarch(2) prototypes in the MD sysarch.h headers. While I'm
at it, use the ANSI C generic pointer type for the second argument,
thus matching the documentation.

Remove the now extraneous (and now conflicting) function declarations
in various libc sources.  Remove now unnecessary casts.

Reviewed by:	bde
2004-01-09 16:52:09 +00:00
Jacques Vidrine
3f6f39ff54 Remove `static' prototype from header file. 2004-01-06 20:36:21 +00:00
Peter Wemm
c15e347e22 GC the unused <machine/kse.h> file. 2003-12-24 00:51:30 +00:00
Alan Cox
35833d6a20 Since we have additional kernel virtual address space, allow the buffer
cache to grow to 400M bytes.
2003-12-20 20:03:10 +00:00
Peter Wemm
d50c65bfce MFi386: remove APIC_IRQ* defines that are no longer used. 2003-12-11 02:48:25 +00:00
David E. O'Brien
70005bdb38 Add just enough of i386/include/pcvt_ioctl.h to amd64/include/pcvt_ioctl.h
such that 'ispcvt' can build.  Unforunately 'ispcvt' is needed in order for
/etc/rc.d/syscons to run.  This fixes the bug where I could not get my
keymap effective at boot.
2003-12-10 02:49:17 +00:00
Alan Cox
4d4a286cba Increase VM_KMEM_SIZE_MAX from 200MB to 400MB.
Discussed with:	peter
2003-12-07 04:51:04 +00:00
Peter Wemm
3db6450423 Reconfigure the runq macros to use the 64 bit ffs/bsf routines instead
of doing a loop and taking two 32 bit passes at the runqueue bits.  All
the 64 bit platforms should probably do this since there are 64 run queues.

Approved by:  re (scottl)
2003-12-06 23:24:18 +00:00
Peter Wemm
176ce2b1f4 Add 64 bit bsf*/ffs* routines. Have the ffs() inline use gcc's builtin
because it uses the better cmove instructions to avoid branches.
2003-12-06 23:22:43 +00:00
Peter Wemm
62b689edc9 Kill the ASM versions of the mtx_lock_spin and friends. They were never
used on amd64, and were actually totally broken.  They had the wrong
calling conventions.  I believe the i386 versions are going away too.

Approved by:  re (scottl)
2003-12-06 23:17:18 +00:00
Peter Wemm
42f5377536 Revert some amd64 changes that cached curthread and converge back to the
i386 version.  The curthread special case in pcpu.h solves my complaint
about the verbose macro expansion in this case.  Note that the i386
version still has some OBE comments, I didn't re-add them back again.

Approved by:  re (scottl)
2003-12-06 23:13:22 +00:00
Peter Wemm
cda078658e Cosmetic and/or trivial sync up with i386.
Approved by:  re (rwatson)
2003-11-21 03:02:00 +00:00
Peter Wemm
b4bae2b0c5 Argh! Followup to previous commit. I checked in the patch with an
unintended local change.  Change Xurthread back to curthread.
2003-11-20 23:49:28 +00:00
Peter Wemm
5dd883833c Provide a streamlined '#define curthread __curthread()' for amd64 to avoid
the compiler having to parse and optimize the PCPU_GET(curthread) so often.
__curthread() is an inline optimized version of PCPU_GET(curthread) that
knows that pc_curthread is at offset zero in the pcpu struct.  Add a
CTASSERT() to catch any possible changes to this.  This accounts for
just over a 1% wall clock speedup for total kernel compile/link time,
and 20% compile time speedup on some specific files depending on which
compile options are used.

Approved by:  re (jhb)
2003-11-20 22:54:44 +00:00
Peter Wemm
0d2a298904 Initial landing of SMP support for FreeBSD/amd64.
- This is heavily derived from John Baldwin's apic/pci cleanup on i386.
- I have completely rewritten or drastically cleaned up some other parts.
  (in particular, bootstrap)
- This is still a WIP.  It seems that there are some highly bogus bioses
  on nVidia nForce3-150 boards.  I can't stress how broken these boards
  are.  I have a workaround in mind, but right now the Asus SK8N is broken.
  The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed.
- Most of my testing has been with SCHED_ULE.  SCHED_4BSD works.
- the apic and acpi components are 'standard'.
- If you have an nVidia nForce3-150 board, you are stuck with 'device
  atpic' in addition, because they somehow managed to forget to connect the
  8254 timer to the apic, even though its in the same silicon!  ARGH!
  This directly violates the ACPI spec.
2003-11-17 08:58:16 +00:00
Bruce Evans
6a0d1abc5d Fixed pedantic warnings for statement-expressions using __extension__
and by not using a statement-expression for the non-expression
__PCPU_SET().
2003-11-17 04:40:58 +00:00
Bruce Evans
81bbee5996 Fixed a pedantic syntax error (a stray semicolon at the end of
PCPU_MD_FIELDS).
2003-11-17 03:40:41 +00:00
Alan Cox
e45db9b837 - Modify alpha's sf_buf implementation to use the direct virtual-to-
physical mapping.
 - Move the sf_buf API to its own header file; make struct sf_buf's
   definition machine dependent.  In this commit, we remove an
   unnecessary field from struct sf_buf on the alpha, amd64, and ia64.
   Ultimately, we may eliminate struct sf_buf on those architecures
   except as an opaque pointer that references a vm page.
2003-11-16 06:11:26 +00:00
Nate Lawson
b72e9cf526 Add the pc_acpi_id PCPU member. The new acpi_cpu driver uses this to
dereference the softc.
2003-11-15 18:58:29 +00:00
Peter Wemm
1f6c75db0b Preemptively burn a bridges. The isa timer code is likely to be
replaced by the HPET timer at some point, so dont even make a release
with the aquire/release_timer0 functions.
2003-11-14 22:34:43 +00:00
Peter Wemm
7b66b81ee4 Convert a couple of pointers to integers for source compatability with
amd64.
2003-11-14 22:23:30 +00:00
Peter Wemm
40e3826a9f Whitespace nit (sorry, couldn't help it) 2003-11-14 22:21:30 +00:00
John Baldwin
3ab2ba59f4 Shuffle the APIC interrupt vectors around a bit:
- Move the IPI and local APIC interrupt vectors up into the 0xf0 - 0xff
  range.  The pmap lazyfix IPI was reordered down next to the TLB
  shootdowns to avoid conflicting with the spurious interrupt vector.
- Move the base of APIC interrupts up 16 so that the first 16 APIC
  interrupts do not overlap the vectors used by the ATPIC.
- Remove bogus interrupt vector reservations for LINT[01].
- Now that 0xc0 - 0xef are available, use them for device interrupts.
  This increases the number of APIC device interrupts to 191.
- Increase the system-wide number of global interrupts to 191 to catch up
  to more APIC interrupts.

Requested by:	peter (2)
2003-11-14 19:10:13 +00:00
John Baldwin
69487322d8 Fix a typo. 2003-11-13 16:41:07 +00:00
John Baldwin
bd9cd7e3f7 - Move manipulation of td_intr_nesting_level out of assembly interrupt
vector stubs and into the C functions they call.
- Move disabling and EOIing of interrupt sources out of PIC driver entry
  points and into intr_execute_handlers().  Intr_execute_handlers() only
  disables a source for an interrupt if it is a stray interrupt or has
  threaded handlers.  Sources with fast handlers no longer disable (mask)
  the source while executing the handlers.
- Move the setting of clkintr_pending into intr_execute_handlers() and set
  the variable for any interrupt source with a vector of 0.  (Should only
  be true for IRQ 0.)  This fixes clkintr_pending in the NO_MIXED_MODE
  case.
- Implement lapic_eoi() and use it to implement ioapic_eoi_source().
- Rename atpic_sched_ithd() to atpic_handle_intr() since it is used to
  handle all atpic interrupts and not just threaded ones.

Inspired by:	peter's changes to amd64 in p4 (1)
Requested by:	bde (2)
2003-11-12 18:13:57 +00:00
Peter Wemm
fcfe57d640 Update the graffiti. 2003-11-08 04:39:22 +00:00
Peter Wemm
398dbb11d8 Switch from having a fpu "device" to something that is more like the
integrated part of the cpu core that it is.
2003-11-08 04:37:54 +00:00
Peter Wemm
bf2f09ee97 The great s/npx/fpu/gi 2003-11-08 03:33:38 +00:00
Peter Wemm
8b2454d833 Rename npx* to fpu*. I haven't done the flags/function names yet. 2003-11-08 02:39:46 +00:00
Scott Long
eb3b7bf69f Document the lockfunc and lockfuncarg arguments to bus_dma_tag_create() in
the busdma headers.
2003-11-07 23:29:42 +00:00
John Baldwin
8f8914ad98 Add the MP Table APIC enumerator. This code uses the BIOS MP Table to
enumerate I/O APICs as well as local APICs.  It also provides Host-PCI
and PCI-PCI bridge drivers to use the MP Table to route PCI interrupts.
2003-11-03 22:12:37 +00:00
John Baldwin
6f92bdd0c1 New APIC support code:
- The apic interrupt entry points have been rewritten so that each entry
  point can serve 32 different vectors.  When the entry is executed, it
  uses one of the 32-bit ISR registers to determine which vector in its
  assigned range was triggered.  Thus, the apic code can support 159
  different interrupt vectors with only 5 entry points.
- We now always to disable the local APIC to work around an errata in
  certain PPros and then re-enable it again if we decide to use the APICs
  to route interrupts.
- We no longer map IO APICs or local APICs using special page table
  entries.  Instead, we just use pmap_mapdev().  We also no longer
  export the virtual address of the local APIC as a global symbol to
  the rest of the system, but only in local_apic.c.  To aid this, the
  APIC ID of each CPU is exported as a per-CPU variable.
- Interrupt sources are provided for each intpin on each IO APIC.
  Currently, each source is given a unique interrupt vector meaning that
  PCI interrupts are not shared on most machines with an I/O APIC.
  That mapping for interrupt sources to interrupt vectors is up to the
  APIC enumerator driver however.
- We no longer probe to see if we need to use mixed mode to route IRQ 0,
  instead we always use mixed mode to route IRQ 0 for now.  This can be
  disabled via the 'NO_MIXED_MODE' kernel option.
- The npx(4) driver now always probes to see if a built-in FPU is present
  since this test can now be performed with the new APIC code.  However,
  an SMP kernel will panic if there is more than one CPU and a built-in
  FPU is not found.
- PCI interrupts are now properly routed when using APICs to route
  interrupts, so remove the hack to psuedo-route interrupts when the
  intpin register was read.
- The apic.h header was moved to apicreg.h and a new apicvar.h header
  that declares the APIs used by the new APIC code was added.
2003-11-03 21:53:38 +00:00
John Baldwin
ecee5704ed New device interrupt code. This defines an interrupt source abstraction
that provides methods via a PIC driver to do things like mask a source,
unmask a source, enable it when the first interrupt handler is added, etc.
The interrupt code provides a table of interrupt sources indexed by IRQ
numbers, or vectors.  These vectors are what new-bus uses for its IRQ
resources and for bus_setup_intr()/bus_teardown_intr().  The interrupt
code then maps that vector a given interrupt source object.  When an
interrupt comes in, the low-level interrupt code looks up the interrupt
source for the source that triggered the interrupt and hands it off to
this code to execute the appropriate handlers.

By having an interrupt source abstraction, this allows us to have different
types of interrupt source providers within the shared IRQ address space.
For example, IRQ 0 may map to pin 0 of the master 8259A PIC, IRQs 1
through 60 may map to pins on various I/O APICs, and IRQs 120 through
128 may map to MSI interrupts for various PCI devices.
2003-11-03 21:25:52 +00:00
John Baldwin
63239aa581 Always export r_gdt and r_idt and give them extern declarations in
machine/segments.h.
2003-10-30 21:42:17 +00:00
John Baldwin
07930cce05 A few whitespace and comment tweaks. 2003-10-24 21:02:26 +00:00
Peter Wemm
cedb3695c1 Add __va_copy and make it always visible, in spite of the __ISO_C_VISIBLE
setting.  Make va_copy be an alias if __ISO_C_VISIBLE >= 1999.

Why?  more than a few ports have an autoconf that looks for __va_copy
because it is available on glibc.  It is critical that we use it if
at all possible on amd64.  It generally isn't a problem for i386 and its
ilk because autoconf driven code tends to fall back to an assignment.
2003-10-24 02:50:39 +00:00
Peter Wemm
63f2bb5ff1 Use a more robust API altogether for the amd64_get_fsbase() etc functions. 2003-10-23 06:06:14 +00:00
Peter Wemm
c0432d033e Renumber the sysarch vectors for amd64 specific syscalls so that I can
implement i386 compat numbers where it makes sense.  This would save a
syscall translation layer.  Yes, this breaks the abi slightly again, but
fortunately its just a recompile rather than tweaking the source.  I will
be fixing the libc stubs while I'm here.
2003-10-23 05:31:23 +00:00