Commit Graph

12 Commits

Author SHA1 Message Date
Olivier Houchard
0769e20256 #if => #ifdef 2006-07-17 21:20:00 +00:00
Olivier Houchard
22e1aadef7 Add a comment explaining why the OHCI mapping has been commented out. 2006-07-15 00:09:53 +00:00
Warner Losh
546bbbb56f MFp4:
Introduce framework to configure the multiplexed pins on boot.

	Since the USART supprots RS-485 multidrop mode, it allows the
	TX pins to float.  However, for RS-232 operations, we don't
	want these pins to float.  Instead, they should be pulled up
	to avoid mismatches.  Linux does something similar when it
	configures the TX lines.  This implies that we also allow the
	RX lines to float rather than be in the state they are left in
	by the boot loader.  Since they are input pins, I think that
	this is the right thing to do.

	Plus minor for our board.
2006-07-14 22:22:57 +00:00
Olivier Houchard
8f395fae42 Comment out the mapping of the OHCI controller registers va == pa. This
address is in the userland address space. The proper thing is either to choose
a virtual address in the kernel address space beyond the KVA, or to use
pmap_mapdev().
2006-07-12 00:48:50 +00:00
Warner Losh
c0386612b8 Compute physmem so we can print it correctly on boot.
Slightly optimize while I'm here.
2006-06-20 23:40:04 +00:00
Warner Losh
57dc2664ef Probe the memory size of the board better. Look at the bus width,
number of banks, rows and columns the SDRAMC is programmed to access
to determine the RAM size for the board, rather than hard-wiring it to
be 32MB.  My company's board with 64MB now probes correctly, as does
the KB9202 with only 32MB.  This means that to detect the right memory
size, our boot loader must correctly initialize these values.  This is
a fairly safe assumption because the boot loader has to initialize
SDRAM already, and it isn't really possible to change this register
after we've accessed SDRAM.
2006-06-20 20:13:40 +00:00
Olivier Houchard
9464ffd0a4 MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to be
able to boot fat kernels.
2006-06-12 22:57:24 +00:00
Warner Losh
3dcdad9a11 Remove sa1_cache_clean_addr. It isn't needed.
Submitted by: kevlo
2006-06-07 05:36:10 +00:00
Olivier Houchard
5207a211b3 MFp4: Don't force single-user now we can go multi-user.
Call cninit() only after the pagetable has been set, as locore.S won't
map the system device for us anymore.
2006-03-22 22:31:31 +00:00
Olivier Houchard
a1de0396bd MFp4: teach the KB920x bits how to know where the ELF trampoline puts the
strtab and the symtab.
2006-03-22 21:16:51 +00:00
Warner Losh
1b0561a15d Add ohci controller mapping. 2006-03-18 01:43:54 +00:00
Warner Losh
1248f2322b Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC
is a ARM920T based CPU with a bunch of built-in peripherals.  The
inital import supports the SPI bus, the TWI bus (although iicbus
integration is not complete), the uarts, the system timer and the
onboard ethernet.  Support for the Kwikbyte KB9202
(http://www.kwikbyte.com) board is also included, although there's no
reason why the 9200 and the 9201 wouldn't also work.  Primitive
support for running under the skyeye emulator is also provided
(although skyeye's support for the AT91RM9200 is a little weak).

The code has been structured so that other members of Atmel's arm family can
be supported in the future.  The AT91SAM9260 is not presently supported
due to lack of hardware.  The arm7tdmi families are also not supported
becasue they lack an MMU.

Many thanks to cognet@ for his help and assistance in bringing up this
board.  He did much of the vm work and wrote parts of the uart and
system timer code as well as the bus space implementation.

The system boots to single user w/o problem, although the serial
console is a little slow and the ethernet driver is still in flux.

This work was sponsored by Timing Solutions, Corporation.  I am
grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00