Commit Graph

401 Commits

Author SHA1 Message Date
Gleb Smirnoff
c6499eccad Mechanically substitute flags from historic mbuf allocator with
malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
Pyun YongHyeon
fe26ad88e3 Add preliminary support for BCM57766 ASIC.
While I'm here add BCM57762 device id which is found on Apple
Thunderbolt ethernet.

Tested by:	Richard Kuhns < rjk <> wintek dot com >
2012-11-30 01:38:00 +00:00
Dimitry Andric
29658c96ce Remove duplicate const specifiers in many drivers (I hope I got all of
them, please let me know if not).  Most of these are of the form:

static const struct bzzt_type {
	[...list of members...]
} const bzzt_devs[] = {
	[...list of initializers...]
};

The second const is unnecessary, as arrays cannot be modified anyway,
and if the elements are const, the whole thing is const automatically
(e.g. it is placed in .rodata).

I have verified this does not change the binary output of a full kernel
build (except for build timestamps embedded in the object files).

Reviewed by:	yongari, marius
MFC after:	1 week
2012-11-05 19:16:27 +00:00
Pyun YongHyeon
84c168f49a TCP/UDP checksum offloading feature for IP fragmented datagram was
removed in r99417.  bge(4) controllers can do TCP checksum offload
for IP fragmented datagrams but unlike ti(4), it lacks UDP checksum
offloading for IP fragmented datagrams. The problem was bge(4)
blindly requested TCP/UDP checksum for IP fragmented datagrams such
that it resulted in corrupted UDP datagrams before r99417.
Remove remaining code for TCP checksum offloading for IP fragmented
datagrams which should have been removed in r99417.
2012-11-01 06:02:27 +00:00
Pyun YongHyeon
d73ea7c6d3 For fast ethernet controllers, Ethernet@WireSpeed is not defined so
explicitly set BGE_PHY_NO_WIRESPEED flag.
2012-10-24 05:54:17 +00:00
Pyun YongHyeon
70c2071b92 Ethernet@WireSpeed is defined for 1000baseT adapter to establish a
link at a lower speed so enabling it for fiber adapters is wrong.
Fix the issue by setting BGE_PHY_NO_WIRESPEED such that brgphy(4)
wouldn't enable the feature.
While I'm here move PHY specific feature/bug configuration to new
location(just before mii attach) for readability.
2012-10-24 05:22:41 +00:00
Pyun YongHyeon
daeeb75cec Do not hardcode phy address. Multi-port controllers use different phy
address.
2012-10-24 05:00:56 +00:00
Pyun YongHyeon
548c8f1ac2 Add APE firmware support and improve firmware handshake procedure.
This change will enable IPMI access on 5717/5718/5719/5720 and 5761
controllers. Because ASF is not available when APE firmware is
present, bge_allow_asf tunable is ignored when driver detects APE
firmware.  Also bge(4) no longer performs two resets(one blind
reset and the other reset with firmware in mind) in device attach.
Now bge(4) performs a reset with enough information in bge_reset().
The APE firmware also needs special handling to make suspend/resume
work but it was not implemented yet.

With this change, bge(4) should work on any 5717/5718/5719/5720
controllers. Special thanks to Mike Hibler at Emulab who setup
remote debugging on Dell R820. Without his help I couldn't be able
to address several issues happened on Dell Rx20 systems. And many
thanks to Broadcom for continuing to support FreeBSD!

Submitted by:	davidch (initial version)
H/W donated by:	Broadcom
Tested by:	many
Tested on:	Del R820/R720/R620/R420/R320 and HP Proliant DL 360 G8
2012-10-11 06:43:43 +00:00
Pyun YongHyeon
cc085b3609 Rework controller reset procedure. Previously driver saved
BGE_PCI_PCISTATE register before issuing global reset. After
issuing reset, it reads BGE_PCI_PCISTATE register again and
compares the saved register value and current value. It was used to
know whether the global reset operation was completed or not.
Unfortunately, this logic caused several issues on recent BCM5717/
5718/5719 and BCM5720 controllers. It seems APE firmware accesses
some registers while global reset is in progress such that reading
BGE_PCI_PCISTATE register after reset does not yield old pre-reset
state value. This resulted in consuming too much time in global
reset and sometimes it couldn't successfully complete reset.

The BGE_MISCCFG_RESET_CORE_CLOCKS of BGE_MISC_CFG register is
self-clearing bit so driver is able to know the reset completion.
But the core-lock reset will disable indirect/flat/standard access
modes such that driver cannot poll BGE_MISCCFG_RESET_CORE_CLOCKS
bit of BGE_MISC_CFG register. So just wait enough time for
core-clock reset to complete.
Data sheet says driver should wait 100us for PCI/PCI-X devices and
100ms for PCIe devices. I chose 1ms for PCI/PCI-X since this value
was used for many years in bge(4). For PCIe devices, use 100ms as
recommended by data sheet.

bge_chipinit() also cleared BGE_MAC_MODE register which shall clear
firmware configured mode information. I think this will result in
losing ASF/IPMI link in device attachment. Let bge_reset() honor
firmware configured BGE_MAC_MODE register and don't announce driver
is UP in bge_reset(). Firmware should have control over driver until
it's fully initialized by driver.

While I'm here, enable workaround for PCI-X BCM5704 A0 in
bge_reset(). This will prevent internal arbitration logic from
switching to the other DMA engine after a retry cycle.
2012-10-11 05:48:04 +00:00
Pyun YongHyeon
87b8c39061 Remove unnecessary delay. I don't see any comments in data sheet
that requires 10ms delay after device reset.  Because that code was
there from day 1, I guess it was added to give enough settlement
time after updating BGE_MAC_MODE register.
The recommended delay time for BGE_MAC_MODE after updating is 40us
and it was already done in r241219.
2012-10-10 05:43:04 +00:00
Pyun YongHyeon
df4db53856 Fix a long standing VCPU reset sequence bug on BCM5906.
The VCPU(Virtual CPU) of BCM5906 is used to provide a mechanism to
control the bootcode execution and to pick up configuration data
stored inside the EEPROM.
The bootcode of BCM5906 will check the BGE_VCPU_STATUS_DRV_RESET
bit to decide which booting procedure to choose.
Data sheet indicates the VCPU of BCM5906 should set
BGE_VCPU_STATUS_DRV_RESET bit *before* VCPU reset or global reset.
2012-10-10 04:38:29 +00:00
Pyun YongHyeon
ad49eccff0 Do not force PCIe 1.0a mode in device reset on BCM5717 and newer
controllers. BCM5785 does not require PCI 1.0a mode as well during
reset.
2012-10-10 02:35:10 +00:00
Pyun YongHyeon
f846d3a23e Honor PHY type fiber for BCM5717/BCM5718/BCM5719/BCM5720. 2012-10-10 02:21:36 +00:00
Pyun YongHyeon
2246e8c6e8 On PHY write error use hex number to show the value.
Add more comments.
2012-10-10 01:59:53 +00:00
Pyun YongHyeon
48630d79c5 If the maximum payload size is 256 bytes or more, set the DMA write
water mark to 256 bytes.  Otherwise controller will encounter DMA
write under run errors and would result in RX DMA hang. If the
maximum payload size is 128 bytes, the water mark is set to 128
bytes as usual.
While here, set maximum read request size to 2048 for BCM5719/BCM5720.
For other PCIe devices, use 4096. And reprogram the maximum read
request size whenever device reset is performed.
2012-10-10 01:24:02 +00:00
Pyun YongHyeon
e010b05517 Rework device detach. While here, move driver lock/callout
initialization to the beginning of device attach for readability.
2012-10-08 07:33:43 +00:00
Pyun YongHyeon
f7add34cfc Limit applying TX data corruption and FIFO workaround to BCM5719
A0. It's believed BCM5720 does not have the issue.
2012-10-08 07:13:45 +00:00
Pyun YongHyeon
a6e66cd28b Follow Broadcom datasheet:
Delay 100 microseconds after enabling transmit MAC.
 Delay 10 microseconds after enabling receive MAC.
2012-10-05 07:13:21 +00:00
Pyun YongHyeon
9b80ffe78f Add 40 microseconds delay after updating EMAC Mode register as
recommended by Broadcom data sheet.
2012-10-05 06:24:22 +00:00
Pyun YongHyeon
a0a03d1e82 APE firmware touches EMAC Mode and TX/RX MAC Mode registers to keep
the MAC connected to the outside world.  So keep the accesses
atomic.
2012-10-05 03:46:25 +00:00
Pyun YongHyeon
e4146b9510 Don't touch EMAC Mode and TX/RX MAC Mode register when driver is
not running.
2012-10-05 03:35:38 +00:00
Gavin Atkinson
389c8bd51e Align the PCI Express #defines with the style used for the PCI-X
#defines.  This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
  s/PCIR_EXPRESS_/PCIER_/g
  s/PCIM_EXP_/PCIEM_/g
  s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with:	jhb
MFC after:	1 week
2012-09-18 22:04:59 +00:00
Marius Strobl
47f4a4dc9a Take advantage of nitems().
MFC after:	3 days
2012-06-02 19:41:28 +00:00
Pyun YongHyeon
198b3ad636 Remove unnecessary device_printfs.
Pointed out by:	marius
2012-05-31 23:56:10 +00:00
Marius Strobl
749a52693c Try to finally get the point in time at which bge_add_sysctls() is called
right; it needs to be called before bge_can_use_msi() but in turn requires
bge_flags to be properly set.

Submitted by:	yongari
MFC after:	3 days
2012-05-30 20:04:07 +00:00
Pyun YongHyeon
00b6d640df Don't force max payload size to 128. Root complex and Endpoint will
negotiate with each other on the TLP payload size so blindly
forcing the size to 128 can cause a completion error which in turn
will stop device.

Reported by:	Geans Pin < geanspin <> broadcom dot com >
MFC after:	5 days
2012-05-23 03:35:08 +00:00
Pyun YongHyeon
37ee7cc719 Make if_ierrors updated whenever any of the following counters are
updated.
 o Number of times NIC ran out of RX buffer descriptors
 o Number of inbound packet errors
 o Number of inbound packets that were chosen to be discarded
Previously only the discarded packet counter was used to update
if_ierrors.  This change fixes wrong if_ierrors counter on
BCM570[0-4] controllers.  For BCM5705 and later controllers bge(4)
already correctly counted it.

Reported by:	Eugene Grosbein <egrosbein <> rdtc dot ru>
2012-03-12 03:47:30 +00:00
Pyun YongHyeon
ea9c3a30f3 Show PCI bus speed and width as well as running mode of PCI-X
device in device attach.  This would help to narrow down issue to a
specific controller and operating mode of the controller.
While I'm here rename BGE_MISCCFG_BOARD_ID with
BGE_MISCCFG_BOARD_ID_MASK.
2012-03-12 02:42:47 +00:00
Pyun YongHyeon
062af0b00e Add workaround for PCI-X BCM5704 controller that live behind
AMD-8131 PCI-X bridge.  The bridge seems to reorder write access to
mailbox registers such that it caused watchdog timeouts by
out-of-order TX completions.

Tested by:	Michael L. Squires <mikes <> siralan dot org >
Reviewed by:	jhb
2012-03-12 02:09:47 +00:00
Pyun YongHyeon
fdd4579648 After r232403, DMA transactions does not cross 4GB boundary for
all PCI devices.  Remove driver workaround for 4GB boundary issue.
2012-03-10 06:12:14 +00:00
Marius Strobl
8c91aec273 Call bge_add_sysctls() early and especially before bge_can_use_msi() so
r230337 actually has a chance of working and doesn't always unconditionally
disable the use of MSIs.
2012-02-07 20:24:52 +00:00
Pyun YongHyeon
d9fc28e40d Oops, fix logic error introduced in r230337. 2012-01-19 20:28:58 +00:00
Pyun YongHyeon
2ae7f64b45 Rename dev.bge.%d.msi_disable to dev.bge.%d.msi which matches
enable/disable and default it to on.

Suggested by:	jhb
2012-01-19 20:21:59 +00:00
Pyun YongHyeon
5c952e8d1b Introduce a tunable that disables use of MSI.
Non-zero value will use INTx.
2012-01-17 22:15:33 +00:00
Pyun YongHyeon
c0220d815a Destroy DMA tag for jumbo RX buffer in device detach. 2011-12-13 20:31:57 +00:00
Pyun YongHyeon
e3215f766e BCM5720 performance tweak from Broadcom.
o Allow multiple outstanding read requests from non-LSO read DMA engine.
 o Allow 4KB burst length reads for non-LSO frames.
 o Enable 512B burst length reads for buffer descriptors.

Submitted by:	Geans Pin < geanspin <> broadcom dot com >
2011-12-13 20:26:46 +00:00
Marius Strobl
4b7ec27007 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
Ed Schouten
6472ac3d8a Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.
The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.
2011-11-07 15:43:11 +00:00
Pyun YongHyeon
f78094a515 Disable updating InputDiscards counter for BCM5717, BCM5718,
BCM5719 A0 and BCM5720 A0 and add comment why driver does not try
to read it.
2011-10-28 01:10:59 +00:00
Pyun YongHyeon
50515680a8 Add initial BCM5720 support.
Many thanks to Broadcom for continuing support of FreeBSD.

Submitted by:	Geans Pin at Broadcom (initial version)
H/W donated by:	Broadcom
2011-10-28 01:04:40 +00:00
Pyun YongHyeon
941a6e134b Define BGE_FW_HB_TIMEOUT_SEC and remove one more magic value.
bge(4) sends BGE_FW_CMD_DRV_ALIVE command to firmware every 2
seconds.  BGE_FW_CMD_DRV_ALIVE command requires 4 bytes data.  This
data contains timeout value in seconds until the next
BGE_FW_CMD_DRV_ALIVE command.
Broadcom recommends driver set the value 3 times longer than the
interval that it sends BGE_FW_CMD_DRV_ALIVE.  Currently bge(4) uses
3 seconds so probably we have to increase it in future and use
different ALIVE command(e.g. BGE_FW_CMD_DRV_ALIVE3).

No functional changes.
2011-10-27 22:10:52 +00:00
Pyun YongHyeon
9931ba85e3 Rename hard-coded value 1 << 14 with BGE_RX_CPU_DRV_EVENT.
This bit(SW event 7 in publicly available data sheet) is used to
make RX CPU handle a firmware command and the bit is automatically
cleared after RX CPU completed the command.
Generally firmware command takes the following steps.
 1. Write BGE_SRAM_FW_CMD_MB with a command.
 2. Write BGE_SRAM_FW_CMD_LEN_MB with the length of the command in bytes.
 3. Write BGE_SRAM_FW_CMD_DATA_MB with actual command data.
 4. Generate BGE_RX_CPU_EVENT and let firmware handle the command.
 5. Wait for the ACK of the firmware command.

No functional changes.
2011-10-27 21:27:37 +00:00
Pyun YongHyeon
3c20120066 Rename BGE_FW_DRV_ALIVE/BGE_FW_PAUSE to BGE_FW_CMD_DRV_ALIVE/BGE_FW_CMD_PAUSE.
Also add more firmware commands(not used yet).
No functional changes.
2011-10-27 20:54:53 +00:00
Pyun YongHyeon
224f878512 SRAM offset 0x0C04 is used by driver to inform the IPMI/ASF firmware
about the various driver events like load, unload, reset, suspend,
restart, and ioctl operations.
Define driver's event rather than using hard-coded values.  We don't
still send suspend/resume event to firmware.

Previously bge(4) used BGE_SDI_STATUS to send events. Because driver
has to access firmware mail box to inform current state, using
BGE_SDI_STATUS register was wrong. The end result was the same as
BGE_SDI_STATUS is 0x0C04.

No functional changes.
2011-10-26 23:52:02 +00:00
Pyun YongHyeon
3fed2d5d77 Offset 0x6810 is RX-RISC event register. Rename BGE_CPU_EVENT with
BGE_RX_CPU_EVENT for readability.
Additionally define BGE_TX_CPU_EVENT for TX-RSIC event register(BCM570[0-4] only).
2011-10-26 23:22:32 +00:00
Pyun YongHyeon
7363541837 Define MAC address mail box and use it instead of using
hard-coded value.
2011-10-26 21:11:40 +00:00
Pyun YongHyeon
888b47f0c7 Rename definition of BGE_SOFTWARE_GENCOMM_* to more readable ones.
The origin of GENCOMM seems to come from Alteon Tigon Host/NIC
interface definition where it defines general communications region
which is active when firmware is loaded and running.  This region
was used in communication between the host and processor internal
to the Tigon chip.
Broadcom data sheet also defines the region as 'Software Gencomm'
in NetXtreme memory map but lacks detailed description of its
interface so it was hard to know which ones are used for which
interface.
This change shall slightly enhance readability.

No functional changes.
2011-10-26 21:05:45 +00:00
Pyun YongHyeon
a7fcfcf3ba BCM5719 cannot handle DMA requests for DMA segments that have
larger than 4KB in size.  However the maximum DMA segment size
created in DMA tag is 4KB, so we wouldn't encounter the issue here.
Just record this issue such that let developers not to create a DMA
segment that is larger than 4KB for BCM5719. It's possible to split
a DMA segment into multiple smaller ones in run time but I believe
it's not worth to implement that.
2011-10-26 18:37:02 +00:00
Pyun YongHyeon
d9820cd85e Broadcom says BCM5755 or higher and BCM5906 have short DMA bug.
Apply workaround to these controllers.
2011-10-26 18:27:01 +00:00
Pyun YongHyeon
d462212405 It is known that all Broadcom controllers have 4GB boundary DMA
bug.  Apply workaround to all controllers.
2011-10-26 18:19:50 +00:00