Commit Graph

4 Commits

Author SHA1 Message Date
Marius Strobl
b09c4bd47a - Merge the *_SET macros from fire(4) which generally print out the
register changes when compiled with SCHIZO_DEBUG and take advantage
  of them.
- Add support for the XMITS Fireplane/Safari to PCI-X bridges. I tought
  I'd need this for a Sun Fire 3800, which then turned out to not being
  equipped with such a bridge though. The support for these should be
  complete but given that it hasn't actually been tested probing is
  disabled for now.
  This required a way to alter the XMITS configuration in case a PCI-X
  device is found further down the device tree so the sparc64 specific
  ofw_pci kobj was revived with a ofw_pci_setup_device method, which is
  called by the ofw_pcibus code for every device added.
- A closer inspection of the OpenSolaris code indicates that consistent
  DMA flushing/syncing as well as the block store workaround should be
  applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around
  interrupt handlers for devices behind PCI-PCI bridges only as suggested
  by the documentation (code for the latter actually exists in OpenSolaris
  but is disabled by default), which also makes more sense.
- Add a workaround for Casinni/Skyhawk combinations. Chances are that
  this solves the crashes seen when using the the on-board Casinni NICs
  of Sun Fire V480 equipped with centerplanes other than 501-6780 or
  501-6790. This also takes advantage of the ofw_pci_setup_device method.
- Mark some unused parameters as such.
2011-03-26 16:49:12 +00:00
Marius Strobl
3eb0900b32 - Enable DMA write parity error interrupts on Schizo with a working
implementation.
- Revert the Sun Fire V890 WAR of r205254. Instead let schizo_pci_bus()
  only panic in case of fatal errors as the interrupt triggered by the
  error the firmware of these and also Sun Fire 280R with version 7
  Schizo caused may happen as late as using the HBA and not only prior
  to touching the PCI bus (in the former case the actual error still is
  fatal but we clear it before touching the PCI bus).
  While at it count and export non-fatal error interrupts via sysctl(9).
- Remove unnecessary locking from schizo_ue().
2010-05-14 20:00:21 +00:00
Marius Strobl
1191b0a44b - According to OpenSolaris, CDMA flushing/syncing for Tomatillos
and XMITS has to be basically done in the same manner as for
  the Sabres, i.e. only for devices behind PCI-PCI-bridges and
  after a PIO read on the far side of the farest PCI-PCI-bridge.
  Given that the Tomatillo documentation mentions no difference
  to the Schizo bridges in this regard and this is also still
  part of the procedure described Schizo documentation this
  seems about right so adjust accordingly (the unconditional
  CDMA flushing/syncing previously done was based on how Linux
  behaves).
- Implement CDMA flushing/syncing for Schizo version >= 5,
  which requires the workaround described in Schizo Errata I-23.
  According to Schizo Errata I-13 it's just unusable with
  version < 5 though. [1]
- Don't register the Schizo streaming buffer for now until it's
  usage is sorted out according to the erratas.
- Register our interrupt filters with the revived INTR_FAST so
  they these interrupts can even interrupt filters of device
  drivers as necessary.
- Remove the comment regarding lack of newbus'ified bus_dma(9)
  as being able to associate a DMA tag with a device would
  allow to implement CDMA flushing/syncing in bus_dmamap_sync(9)
  but that would totally kill performance. Given that for devices
  not behind a PCI-PCI bridge the host-to-PCI bridges also only
  do CDMA flushing/syncing based on interrupts there's no
  additional disadvantage for polling(4) callbacks in the case
  schizo(4) has to do the CDMA flushing/syncing but rather a
  general problem.

Reported by:	Michael Moll [1]
2008-11-20 18:44:09 +00:00
Marius Strobl
20284fcdd9 Add a driver for Schizo' Fireplane/Safari to PCI 2.1 and Tomatillo'
JBus to PCI 2.2 bridges. In theory, this driver should also handle
`XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access
to such hardware, support for these hasn't be fleshed out, yet.
2008-09-28 00:07:05 +00:00