Commit Graph

12 Commits

Author SHA1 Message Date
Sam Leffler
d212022417 Merge WIP from p4:
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
  to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
  - IDE compact flash
  - MCU
  - front panel LED on i2c bus
  - Octal LED latch

Sanity-tested with NFS-root on Avila and Cambria boards.  Requires
pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
Rafal Jaworowski
373bbe25ff Introduce basic support for Marvell families of system-on-chip ARM devices:
*  Orion
     - 88F5181
     - 88F5182
     - 88F5281

  * Kirkwood
     - 88F6281

  * Discovery
     - MV78100

The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:

  * GPIO
  * Interrupt controller
  * L1, L2 cache
  * Timers, watchdog, RTC
  * TWSI (I2C)
  * UART

Other peripherals drivers will be introduced separately.

Reviewed by:	imp, marcel, stass (Thanks guys!)
Obtained from:	Marvell, Semihalf
2008-10-13 20:07:13 +00:00
Rafal Jaworowski
f4e42148d7 ARM interrupts improvements.
- Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling
  arm_setup_irqhandler() in loop is bogus, as there's just one cookie given
  from the caller and it is overwritten in each iteration so that only the
  last handler's cookie value prevails.

- Proper intr masking/unmasking handling: the IRQ source is masked at PIC level
  only after the last handler has been removed from the list.

Reviewed by:	cognet, imp, sam, stass
Obtained from:	Grzegorz Bernacki gjb ! semihalf dot com
2008-09-11 12:36:13 +00:00
Benno Rice
9722a61504 Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connex
boards.  This is enough to net-boot to multiuser.

Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC
add-on boards.

I'll be putting some instructions on how to boot this on the Gumstix boards
online soon.

This is still fairly rough and will be refined over time but I felt it was
better to get this out there where other people can help out.
2008-06-06 05:08:09 +00:00
Olivier Houchard
e19357d3a5 On the AT91, we need to write on the EOI register after we handle an
interrupt. So, add a new function pointer, arm_post_filter, which defaults
to NULL, and which will be used as the post_filter arg for
intr_event_create(). Set it properly for the AT91, so that it boots again.

Reported by:	hps
2008-04-20 23:29:06 +00:00
Olivier Houchard
d076bcf203 The iop34x has 128 interrupts. 2007-06-16 15:03:33 +00:00
Paolo Pisati
ef544f6312 o break newbus api: add a new argument of type driver_filter_t to
bus_setup_intr()

o add an int return code to all fast handlers

o retire INTR_FAST/IH_FAST

For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current

Reviewed by: many
Approved by: re@
2007-02-23 12:19:07 +00:00
Olivier Houchard
f60e923b23 - MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32
interrupts.
- Implement teardown methods where appropriate.
2005-06-09 12:26:20 +00:00
Olivier Houchard
31d0686d2d Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides
64 irqs.
This should be re-thought later.
2005-02-13 18:26:31 +00:00
Warner Losh
d8315c79d9 Start all license statements with /*- 2005-01-05 21:58:49 +00:00
Olivier Houchard
7c320e5bfb Add new functions to know which irqs are pending, and to mask and unmask
interrupts, as these are CPU specific.
If the interrupt handler is not marked as INTR_FAST, don't unmask the
interrupt until it as been serviced.
2004-09-23 22:09:57 +00:00
Olivier Houchard
6fc729af63 Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00