hardware but lack the larger fifos rev 5 hardware should have.
The linux world (where our FDT data comes from) solved this by adding
a new property to pl011 nodes, "arm,primecell-periphid". When this
property is present, its values override the values in the hardware
periphid registers. For pl011 rev 5 hardware with small fifos, they
override the id so that it appears to be rev 4 hardware.
The driver now uses the new property when present. It also continues
to check the device compat string, to handle older fdt data that may
still be in use on existing systems (on RPi systems it is common to
update system software without updating fdt data which is part of the
boot firmware).
Reviewed by: imp
Starting with rev 5 (which is inexplicably indicated by a version number
of '3' in the Peripheral ID register), the pl011 doubled the size of the
rx and tx fifos, to 32 bytes, so read the ID register and set the size
variables in the softc accordingly.
An interesting wrinkle in this otherwise-simple concept is that the
bcm2835 SoC, used in Raspberry Pi systems among others, has the rev 5
pl011 hardware, but somehow also has the older 16-byte fifos. We check
the FDT data to see if the hardware is part of a bcm283x system and use
the smaller size if so.
Thanks to jchandra@ for pointing out that newer hardware has bigger fifos.
have been in the code all along, but were masked by having a fifo depth of
one byte at the hardware level, so everything kinda worked by accident.
The hardware interrupts when the TX fifo is half empty, so set
sc->sc_txfifosz to 8 bytes (half the hardware fifo size) to match. This
eliminates dropped characters on output.
Restructure the read loop to consume all the bytes in the fifo by using
the "rx fifo empty" bit of the flags register rather than the "rx ready"
bit of the interrupt status register. The rx-ready interrupt is cleared
when the number of bytes in the fifo fall below the interrupt trigger
level, leaving the fifo half full every time receive routine was called.
Now it loops until the fifo is completely empty every time (including
when the function is called due to a receive timeout as well as for
fifo-full).
The pl011 UART has a 16 entry Tx FIFO and a 16 entry Rx FIFO that
have not been used so far. Update the driver to enable the FIFOs
and use them in transmit and receive.
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D8819
Remove unused fields from uart_pl011_softc. Add an interrupt mask
field to the softc and use it to set the interrupt mask register.
There should be no functional change introduced here except in the
grab and ungrab functions. In these functions, we now disable and
enable all interrupts rather than just the receive interrupt.
Clear the interrupt state before reading the input char from the
input FIFO. In the current code there is a window between the read
to the data register and the write to the the ICR, during which an
input char will not cause an interrupt.
This fixes the issue by which the serial port input on QEMU freezes
when using the emulated pl011 serial port.
the uart class to use in a similar way as the fdt driver.
Obtained from: ABT Systems Ltd
MFC after: 1 month
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D7248
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.
This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.
MFC after: 1 week
uart implementations, and export them using the new linker-set mechanism.
Differential Revision: https://reviews.freebsd.org/D1993
Submitted by: Michal Meloun
is the case, depending on the options, in some of the ARM hardware
simulators. In these cases we don't get an interrupt so will need to
schedule the task to write more data to the uart.
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Instead of waiting for empty TX FIFO it is more reasonable to
block on full FIFO. As soon as FIFO slot is free the character
can be transmitted.
In case of TX FIFO disabled, TXFF bit indicates that transmit
register is not empty.
Obtained from: Semihalf
Reviewed by: andrew, emaste
Sponsored by: The FreeBSD Foundation
console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.
Should have been part of r260889, but waasn't due to command line typo.
Reviewed by: bde (with reservations)
uart(4) allocates send and receiver buffers in attach() before it calls
the low-level driver's attach routine. Many low-level drivers set the
fifo sizes in their attach routine, which is too late. Other drivers set
them in the probe() routine, so that they're available when uart(4)
allocates buffers. This fixes the ones that were setting the values too
late by moving the code to probe().
