Commit Graph

11 Commits

Author SHA1 Message Date
Andrew Turner
83fb1bdbfe Rename smmu pmap functions
These are SMMU (and MALI GPU) specific. Give them a SMMU specific name.

Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D38948
2023-03-16 16:45:42 +00:00
Ruslan Bukin
4b4e8cb53a smmu: set guest address space range to 48-bit, which is a hardware
limit in our configuration.

Reviewed by:	andrew
Sponsored by:	UKRI
Differential Revision:	https://reviews.freebsd.org/D37756
2022-12-21 15:53:05 +00:00
Ruslan Bukin
41ce5498f8 Add OFW support to arm64's IOMMU framework.
This is needed to support non-PCI devices like memory-mapped
display controllers.
Split-out some initialization code from iommu_ctx_alloc() into
iommu_ctx_init() method so we could pass controller's MD-data
obtained from DTS to the driver prior to a CTX initialization.

Tested on Morello SoC.

Sponsored by:	UKRI
2022-05-18 14:11:23 +01:00
Ruslan Bukin
182a69328d Fix stream table entry (STE) initialization and removal.
For PCI devices we have entire L1 descriptor for every session ID (SID),
but for non-PCI (e.g. Display Processing Unit DPU), a single L1
descriptor serves multiple SIDs.
So prevent re-initialization of L1 descriptor if already initialized.
Don't free entire L1 descriptor on every STE removal.

Sponsored by:	UKRI
2022-05-18 13:42:37 +01:00
Ruslan Bukin
1cb8e38e4b Code deduplication: use SID-getting functions in smmu_find().
Sponsored by:	UKRI
2022-05-10 16:20:15 +01:00
Ruslan Bukin
b7fca06bbf Split-out SID-getting code to a separate functions.
Also ensure we are dealing with PCI-class devices.

Sponsored by:	UKRI
2022-05-09 20:13:57 +01:00
Ruslan Bukin
f224006fe1 Allocate resources selectively.
One of the SMMU interrupt lines (priq) is optional and may be ommited in FDT.

Tested on ARM Morello Board, which has three SMMU units: first two have four
interrupt lines, last one has three interrupt lines.

Sponsored by: UKRI
2022-05-09 13:30:37 +01:00
Ruslan Bukin
0a8e88fa73 Change __unused to __diagused.
Pointed out by:	jhb
Sponsored by:	UKRI
2022-05-09 11:24:47 +01:00
Ruslan Bukin
a5ec261a7c Add FDT attachment driver for ARM System MMU v3.2 controller.
Tested on ARM Morello Board.

Sponsored by:	UKRI
2022-05-07 11:18:35 +01:00
Ruslan Bukin
f17c4e38f5 Move IOMMU code to a separate pmap module and switch ARM System MMU
driver to use it.

Add ARM Mali Txxx (Midgard), Gxx (Bifrost) GPU page management code.

Sponsored by: UKRI
2021-04-27 19:16:09 +01:00
Ruslan Bukin
4cc8701067 Introduce IOMMU support for arm64 platform.
This adds an arm64 iommu interface and a driver for Arm System Memory
Management Unit version 3.2 (ARM SMMU v3.2) specified in ARM IHI 0070C
document.

Hardware overview is provided in the header of smmu.c file.

The support is disabled by default. To enable add 'options IOMMU' to your
kernel configuration file.

The support was developed on Arm Neoverse N1 System Development Platform
(ARM N1SDP), kindly provided by ARM Ltd.

Currently, PCI-based devices and ACPI platforms are supported only.
The support was tested on IOMMU-enabled Marvell SATA controller,
Realtek Ethernet controller and a TI xHCI USB controller with a low to
medium load only.

Many thanks to Konstantin Belousov for help forming the generic IOMMU
framework that is vital for this project; to Andrew Turner for adding
IOMMU support to MSI interrupt code; to Mark Johnston for help with SMMU
page management; to John Baldwin for explaining various IOMMU bits.

Reviewed by:	mmel
Relnotes:	yes
Sponsored by:	DARPA / AFRL
Sponsored by:	Innovate UK (Digital Security by Design programme)
Differential Revision:	https://reviews.freebsd.org/D24618
2020-11-16 21:55:52 +00:00