268f0ea9a3
7 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Justin T. Gibbs
|
cd036e891a |
ahc_pci.c:
If bus_dma will give us addresses > 32 bits, setup our dma tag to accept up to 39bit addresses. aic7770.c: Update the softc directly rather than use an intermediate "probe_config" structure. aic7xxx.c: Complete core work to support 39bit addresses for bulk data dma operations. Controller data structures still must reside under the 4GB boundary to reduce code/data size in the sequencer and related data structures. This has been tested under Linux IA64 and will be tested on IA64 for FreeBSD as soon as our port can run there. Add bus dmamap synchronization calls around manipulation of all controller/kernel shared host data structures. Implement data pointer reinitialation for a second data phase in a single connection in the kernel rather than bloat the sequencer. This is an extremely rare operation (does it ever happen?) and the sequencer implementation was flawed for some of the newest chips. Don't ever allow our target role to initiate a PPR. This is forbidden by the SCSI spec. Add a few missing endian conversions in the ignore wide pointers code. The core has been tested on the PPC under Linux and should work for FreeBSD PPC. As soon as I can test the OSM layer for FreeBSD PPC, I will. Move some of ahc_softc_init() into ahc_alloc() now that the probe_config structure is gone. Add a 4GB boundary condition on all of our dma tags. 32bit DAC under PCI only works on a single 4GB "page". Although we can cross 4GB on a true 64bit bus, the card won't always be installed in one and we can save code space and cost in implementing high address support by assuming the high DWORD address will never change. Add diagnostics to ahc_search_qinfifo(). Correct a target mode issue with bus resets. To avoid an interrupt storm from a malicious third party holding the reset line, the sequencer would defer re-enabling the reset interrupt until either a select-out or select-in. Unfortunately, the select-in enable bit is cleared by a bus reset, so a second reset will render the card deaf to an initiator's attempts to contact it. We now re-enable bus reset interrupts immediately if the target role is enabled. aic7xxx.h: Remove struct ahc_probe_config. SCB's now contain a pointer to the sg_map_node so we can perfrom bus dma sync operations on the SG list prior to queuing a command. aic7xxx.reg: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Add the DSCOMMAND1 register which is used to access the high DWORD of address bits. Add the data pointer reinitialize sequencer interrupt code. aic7xxx.seq: Register the Perforce ID for this file with the VERSION keyword so it is printed in generated files. Remove code to re-enable the bus reset interrupt after a select-in. In target mode we cannot defer this operation as ENSELI is cleared by a bus reset. Complete 39bit support. Generate a sequencer inteerrupt rather than handle the data pointers re-initialitation in the sequencer. Inline the "seen identify" assertion to save a few cycles. Short circuit the update of our residual data if we have fully completed a transfer. The residual is correct from our last S/G load operation. Short circuit full SDPTR processing if the residual is 0. Just mark the transfer as complete. aic7xxx_93cx6.c: Synchronize perforce IDs. aic7xxx_freebsd.c: Complete untested 39bit support. Add missing endia conversions. Clear our residuals prior to starting a command. The update residual code in the core only sets the residual if there is one. aic7xxx_freebsd.h: Modeify ahc_dmamap_sync() macros to take an offset and a length. This is how sync operations are performed in NetBSD, and we should update our bus dma implementation to match. aic7xxx_inline.h: Add data structure synchronization helper functions. Fix a bug in ahc_intr() where we would not clear our unsolicited interrupt counter after running our PCI interrupt handler. This may have been the cause of the spurious PCI interrupt messages. aic7xxx_pci.c: Adjust for loss of probe_config structure. Guard against bogus 9005 subdevice information as seen on some IBM MB configurations. Add 39bit address support. MFC after: 10 days |
||
|
Justin T. Gibbs
|
58fb7d8e0b |
ahc_eisa.c:
ahc_pci.c:
Prepare for making ahc a module by adding module dependency
and version info.
aic7770.c:
Remove linux header ifdefs. The headers are handled differently
in Linux where local includes (those using "'s instead of <>'s)
are allowed.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
aic7xxx.c:
Remove linux header ifdefs.
current->curr to avoid Linux's use of current as a
#define for the current task on some architectures.
Add a helper function, ahc_assert_atn(), for use in
message phases we handle manually. This hides the fact
that U160 chips with the expected phase matching disabled
need to have SCSISIGO updated differently.
if (ahc_check_residual(scb) != 0)
ahc_calc_residual(scb);
else
ahc_set_residual(scb, 0);
becomes:
ahc_update_residual(scb);
Modify scsi parity error (or CRC error) handling to
reflect expected phase being disabled on U160 chips.
Move SELTO handling above BUSFREE handling so we can
use the new busfree interrupt behavior on U160 chips.
In ahc_build_transfer_msg() filter the period and ppr_options
prior to deciding whether a PPR message is required.
ppr_options may be forced to zero which will effect our
decision.
Correct a long standing but latent bug in ahc_find_syncrate().
We could choose a DT only rate even though DT transfers were
disabled. In the CAM environment this was unlikely as CAM
filters our rate to a non-DT value if the device does not
support such rates.
When displaing controller characteristics, include the
speed of the chip. This way we can modify the transfer
speed based on optional features that are enabled/disabled
in a particular application.
Add support for switching from fully blown tagged queing
to just using simple queue tags should the device reject
an ordered tag.
Remove per-target "current" disconnect and tag queuing
enable flags. These should be per-device and are not
referenced internally be the driver, so we let the OSM
track this state if it needs to.
Use SCSI-3 message terminology.
aic7xxx.h:
The real 7850 does not support Ultra modes, but there are
several cards that use the generic 7850 PCI ID even though
they are using an Ultra capable chip (7859/7860). We start
out with the AHC_ULTRA feature set and then check the
DEVSTATUS register to determine if the capability is really
present.
current -> curr
ahc_calc_residual() is no longer static allowing it to
be called from ahc_update_residual() in aic7xxx_inline.h.
Update some serial eeprom definitions for the latest
BIOS versions.
aic7xxx.reg:
Add a combined DATA_PHASE mask to the SCSIPHASE register
definition to simplify some sequencer code.
aic7xxx.seq:
Take advantage of some performance features available only
on the U160 chips. The auto-ack feature allows us to ack
data-in phases up to the data-fifo size while the sequencer
is still setting up the DMA engine. This greatly reduces
read transfer latency and simplifies testing for transfer
complete (check SCSIEN only). We also disable the expected
phase feature, and enable the new bus free interrupt behavior,
to avoid a few instructions.
Re-arrange the Ultra2+ data phase handling to allow us to
do more work in parallel with the data fifo flushing on a
read.
On an SDTR, ack the message immediately so the target can
prepare the next phase or message byte in parallel with
our work to honor the message.
aic7xxx_93cx6.c:
Remove linux header ifdefs.
aic7xxx_freebsd.c:
current -> curr
Add a module event handler.
Handle tag downgrades in our ahc_send_async() handler.
We won't be able to downgrade to "basic queuing" until
CAM is made aware of this queuing type.
aic7xxx_freebsd.h:
Include cleanups.
Define offsetof if required.
Correct a few comments.
Update prototype of ahc_send_async().
aic7xxx_inline.h:
Implement ahc_update_residual().
aic7xxx_pci.c:
Remove linux header ifdefs.
Correct a few product strings.
Enable several U160 performance enhancing features.
Modify Ultra capability determination so we will enable
Ultra speeds on devices with a 7850 PCI id that happen
to really be a 7859 or 7860.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
|
||
|
Justin T. Gibbs
|
b95de6dafd |
aic7770.c:
aic7xxx_pci.c: Enable board generation of interrupts only once our handler is in place and all other setup has occurred. aic7xxx.c: More conversion of data types to ahc_* names. tmode_tstate and tmode_lstate are the latest victims. Clean up the check condition path by branching early rather than indenting a giant block of code. Add support for target mode initiated sync negotiation. The code has been tested by forcing the feature on for all devices, but for the moment is left inaccesible until a decent mechanism for controlling the behavior is complete. Implementing this feature required the removal of the old "target message request" mechanism. The old method required setting one of the 16 bit fields to initiate negotiation with a particular target. This had the nice effect of being easy to change the request and have it effect the next command. We now set the MK_MESSAGE bit on any new command when negotiation is required. When the negotiation is successful, we walk through and clean up the bit on any pending commands. Since we have to walk the commands to reset the SCSI syncrate values so no additional work is required. The only drawback of this approach is that the negotiation is deferred until the next command is queued to the controller. On the plus side, we regain two bytes of sequencer scratch ram and 6 sequencer instructions. When cleaning up a target mode instance, never remove the "master" target mode state object. The master contains all of the saved SEEPROM settings that control things like transfer negotiations. This data will be cloned as the defaults if a target mode instance is re-instantiated. Correct a bug in ahc_set_width(). We neglected to update the pending scbs to reflect the new parameters. Since wide negotiation is almost always followed by sync negotiation it is doubtful that this had any real effect. When in the target role, don't complain about "Target Initiated" negotiation requests when an initiator negotiates with us. Defer enabling board interrupts until after ahc_intr_enable() is called. Pull all info that used to be in ahc_timeout for the FreeBSD OSM into ahc_dump_card_state(). This info should be printed out on all platforms. aic7xxx.h: Add the SCB_AUTO_NEGOITATE scb flag. This allows us to discern the reason the MK_MESSAGE flag is set in the hscb control byte. We only want to clear MK_MESSAGE in ahc_update_pending_scbs() if the MK_MESSAGE was set due to an auto transfer negotiation. Add the auto_negotiate bitfield for each tstate so that behavior can be controlled for each of our enabled SCSI IDs. Use a bus interrupt handler vector in our softc rather than hard coding the PCI interrupt handler. This makes it easier to build the different bus attachments to the aic7xxx driver as modules. aic7xxx.reg: Remove the TARGET_MSG_REQUEST definition for sequencer ram. aic7xxx.seq: Fix a few target mode bugs: o If MK_MESSAGE is set in an SCB, transition to message in phase and notify the kernel so that message delivery can occur. This is currently only used for target mode initiated transfer negotiation. o Allow a continue target I/O to compile without executing a status phase or disconnecting. If we have not been granted the disconnect privledge but this transfer is larger than MAXPHYS, it may take several CTIOs to get the job done. Remove the tests of the TARGET_MSG_REQUEST field in scratch ram. aic7xxx_freebsd.c: Add support for CTIOs that don't disconnect. We now defer the clearing of our pending target state until we see a CTIO for that device that has completed sucessfully. Be sure to return early if we are in a target only role and see an initiator only CCB type in our action routine. If a CTIO has the CAM_DIS_DISCONNECT flag set, propogate this flag to the SCB. This flag has no effect if we've been asked to deliver status as well. We will complete the command and release the bus in that case. Handle the new auto_negotiate field in the tstate correctly. Make sure that SCBs for "immediate" (i.e. to continue a non disconnected transaction) CTIO requests get a proper mapping in the SCB lookup table. Without this, we'll complain when the transaction completes. Update ahc_timeout() to reflect the changes to ahc_dump_card_state(). aic7xxx_inline.h: Use ahc->bus_intr rather than ahc_pci_intr. |
||
|
Justin T. Gibbs
|
6fb77fef4d |
This is an MFC candidate.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
|
||
|
Justin T. Gibbs
|
64a3876fef | Update Copyright notices for new year. (should have been in last commit). | ||
|
Justin T. Gibbs
|
a5847d5c27 |
ahc_eisa.c:
Initialize rid to 0. This doesn't seem to make any difference (the driver doesn't care what rid it gets and no-one seems to check rid's value), but follows standard conventions. Pass in our device_t to ahc_alloc(). We now use device_T softc storage, so passing NULL results in a panic. Set the unit number in our softc so that the driver core can retrieve it. ahc_pci.c: Set the unit number in our softc so that the driver core can retrieve it. aic7770.c: Insert our softc into the list of softcs when initialization is successful. aic7xxx.c: Remove a workaround for an aic7895 bug we will never trigger. Add additional diagnostic info to ahc_dump_card_state(). Always panic the system if a sequencer assertion fails. AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. Replace a hard coded number with a constant. Guard against looping forever in ahc_pause_and_flushwork(). A hot eject or card failure may make the intstat register return 0xFF, so limit the number of interrupts we'll process. Correct the code in ahc_search_qinfifo() that guarantees that the sequencer will see an abort collision if the qinfifo is modified when a DMA is in progress. We now do this fixup after modifying the queue. This guarantees that the HSCB we place at the head of the queue is not the same as the old head. Using "next hscb" (guaranteed not to be the same as the first SCB) before clearing the queue could free up the original head hscb to be used during a remove operation placing it again at the head of the qinfifo. aic7xxx.h: Reduce the maximum number of outstanding commands to 253 from 254. To handle our output queue correctly on machines that only support 32bit stores, we must clear the array 4 bytes at a time. To avoid colliding with a DMA write from the sequencer, we must be sure that 4 slots are empty when we write to clear the queue. This reduces us to 253 SCBs: 1 that just completed and the known three additional empty slots in the queue that preceed it. Yahoo was able to force this race on one of their systems. Interrupts were disabled for such a time that the entire output queue was filled (254 entries complete without any processing), and our 32bit write to clear the status clobbered one entry. Add a feature tag for devices that are removable. aic7xxx.reg: Never use the sequencer interrupt value of 0xF0. We need to guanrantee that an INTSTAT value of 0xFF can only occur during card failure or a hot-eject. Align the busy targets table with the begining of scratch space. This seems to appease a chip bug in the aic7895. aic7xxx.seq: Be sure to disable select-out after a bus free event that occurs early in a selection. If we don't disable select-out, we will believe that it is enabled even though a new selection will never occur. Move the clearing of SELDI to just before a jump. This appeases another chip bug of the aic7895. Make the target mode command loop a bit more efficient. AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. Properly cleanup the last SCB we tested against should we fail to properly find an SCB for a reselection. Add some additional sequencer debugging code. aic7xxx_freebsd.c: Limit the driver to 253 outstanding commands per adapter. Guard against overflow in timeout handling. aic7xxx_inline.h: AHC_SCB_BTT is a "flag" not a "feature". Check the right field in the softc. aic7xxx_pci.c: Set the removable feature for the apa1480 cardbus and the 29160C Compact PCI card. Don't report high byte termination information for narrow cards. Use a PCI read rather than a questionable delay when fetching/setting termination settings. |
||
|
Justin T. Gibbs
|
717d424718 |
Move aicasm to its own subdirectory.
Separate our platform independent hooks from core driver functionality shared between platforms (FreeBSD and Linux at this time). Add sequencer workarounds for several chip->chipset interactions. Correct external SCB corruption problem on aic7895 based cards (3940AUW). Lots of cleanups resulting from the port to another OS. |