2 Commits

Author	SHA1	Message	Date
Landon J. Fuller	caeff9a3c2	bhnd(4): implement MIPS and PCI(e) interrupt support ... On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518	2017-11-21 23:15:20 +00:00
Landon J. Fuller	8f3bba2d35	[mips/broadcom] Move MIPS-specific bhnd(4) nexus drivers to ... sys/mips/broadcom, and add MIPS/BCM4706-specific workaround to bhnd_nexus_is_hw_disabled() -- the BCM4706 low-cost package leaves secondary GMAC cores floating. Reviewed by: mizhka Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D9499	2017-02-13 19:58:55 +00:00