Commit Graph

28 Commits

Author SHA1 Message Date
Rui Paulo
ecc2d99765 Style changes and typos fixed. 2013-08-19 05:48:42 +00:00
Ian Lepore
87a6a871e2 Allow a hardware driver to pass clock frequencies into the sdhci driver.
The sdhci spec says that if the base or timeout clock frequency in the
capabilities register is zero, the driver must obtain the frequency "from
another source."  This change defines that other source to be the low-level
hardware driver, which can pre-set the frequencies in slot.max_clk and
slot.timeout_clk before calling sdhci_init_slot().

This helps with a growing number of SoCs that have sdhci base clock
frequencies that either won't fit into the range allowed by the number of
bits available in the capabilities register, or the frequency is runtime-
configurable.
2013-08-19 01:29:13 +00:00
Ian Lepore
677ee4943a Add a new SDHCI_QUIRK_DONT_SHIFT_RESPONSE for hardware that pre-shifts
the response bits the way we do in software.  While the hardware is just
doing the sensible thing rather than leaving it to the software, it's in
violation of the spec by doing so.  Grrrr.
2013-08-18 19:08:53 +00:00
Ian Lepore
54c665855d Add named constants for 8-bit bus support. The sdhci and mmc drivers
don't have support for this yet, but some low-level hardware is ready
for it when the higher layers catch up.
2013-08-16 19:44:49 +00:00
Ian Lepore
ceb9e9f70d When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit.  If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.
2013-08-16 19:40:00 +00:00
Wojciech A. Koszek
a9caca6a75 Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by:	Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Reviewed by:	wkoszek, freebsd-arm@ (no objections raised)
2013-04-27 22:38:29 +00:00
Oleksandr Tymoshenko
c3a0f75a9f Add hooks for plugging platform-provided transfer backend.
In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
    to start and finish transfer
- platform_will_handle - check whether transaction is
    suitable for backend. If not - driver will fall back
    to PIO mode.

Submitted by:	Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by:	ian@
2013-02-28 19:43:14 +00:00
Oleksandr Tymoshenko
acbaa69f31 Remove accidentally committed debug panic(9) call 2013-02-17 01:34:25 +00:00
Oleksandr Tymoshenko
7337a22fb0 Disable debug accidentally enabled by previous commit 2013-02-16 23:52:14 +00:00
Oleksandr Tymoshenko
57677a3a4a Various timing-related fixes:
- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
  implementation.  By re-implementing this method hardware
  drivers can control frequency controller operates when
  executing initialization sequence
2013-02-16 23:12:06 +00:00
Sofian Brabez
61bfd86762 Use DEVMETHOD_END macro defined in sys/bus.h instead of {0, 0} sentinel on device_method_t arrays
Reviewed by:	cognet
Approved by:	cognet
2013-01-30 18:01:20 +00:00
Oleksandr Tymoshenko
33aad34de6 - Get proper maximum clock frequency for SDHCI v3.0 and higher 2012-11-30 02:35:13 +00:00
Oleksandr Tymoshenko
8f3b7d5616 Add new quirks:
- Data timeout is broken
  - Data timeout uses SD clock
  - Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0
2012-10-29 17:21:58 +00:00
Oleksandr Tymoshenko
d6b3aaf842 Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface

No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.
2012-10-16 01:10:43 +00:00
Gleb Smirnoff
ba32fa9394 Return back double spacing. 2012-07-30 08:56:56 +00:00
Gleb Smirnoff
1fc2ea61bf Fix typo in comment, should be MHz here.
Submitted by:	Daan Vreeken <Daan vitsch.nl>
2012-07-21 14:07:43 +00:00
Gleb Smirnoff
14d060a6b8 Add support for RICOH R5CE823 card reader, that can be found in
some Lenovo laptops.

The conroller needs a quirk to lower its frequency, and after
that it operates normally.
2012-02-09 10:20:41 +00:00
Ed Schouten
6472ac3d8a Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.
The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.
2011-11-07 15:43:11 +00:00
Jayachandran C.
bcd91d25da Fix read_ivar implementation for MMC and SD.
1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression
'*(int *)result = val' to assign to result which is uintptr_t *.
This does not work on big-endian 64 bit systems.

2. The media_size ivar is declared as 'off_t' which does not fit
into uintptr_t in 32bit systems, change this to long.

Submitted by:	kanthms at netlogicmicro com (initial version)
2011-05-30 06:23:51 +00:00
Pawel Jakub Dawidek
8bfafab1d2 Force DMA for controller found in Lenovo T510 (probably in others too).
This makes reads 10 times faster.

Discussed with:	mav
2011-02-27 13:58:20 +00:00
Alexander Motin
bea2dca299 Add support for interruptless kernel dumping. 2009-02-17 19:12:15 +00:00
Warner Losh
507a69a927 Fix read_ivar prototype. 2009-02-10 23:13:48 +00:00
Alexander Motin
5b69a497e5 Add hw.sdhci.debug sysctl to control debug level. 2009-01-28 22:53:41 +00:00
Alexander Motin
d493985afd Cleanup msleep() arguments.
Move wakeup() out of the lock.
2008-12-06 21:52:32 +00:00
Alexander Motin
d8208d9eb1 Forget current bus power settings on full reset. Chip must be reconfigured.
Do not issue command if there is no card, clock or power.
Controller will not detect command timeout without clock active.
2008-12-06 01:31:07 +00:00
Alexander Motin
92bf0e27a0 Add controller suspend/resume support.
To be able to correctly suspend/resume with card inserted,
respective support should be also implemented at mmc and mmcsd layers.
2008-12-01 17:45:56 +00:00
Alexander Motin
3a4a255741 Allow card reader bridge driver to report maximum supported transfer size.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.

Enable multiblock operations disabled before to follow at91_mci driver
limitations.

Reviewed by:	imp@
2008-10-29 20:01:26 +00:00
Alexander Motin
831f5dcf12 Import sdhci (PCI SD Host Controller) driver.
Driver supports PCI devices with class 8 and subclass 5 according to
SD Host Controller Specification.

Update NOTES, enable module and static build.
Enable related mmc and mmcsd modules build.

Discussed on:   mobile@, current@
2008-10-21 20:33:40 +00:00