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159 Commits

Author SHA1 Message Date
Robert Noland
a80ca4341a vm_offset_t is unsigned, so compare of >= 0 is not needed. 
Found with:	Coverity Prevent(tm)
CID:		2259

MFC after:	3 days
 2009-03-20 18:35:16 +00:00
Robert Noland
0bbcd5ca68 Remove the DRM_ERROR to fix build. It didn't make any sense anyway. 
MFC after:	3 days
 2009-03-20 18:01:32 +00:00
Robert Noland
c8264c8ee2 Fix what appears to be a typo, and restore the registers correctly. 
Found with:	Coverity Prevent(tm)
CID: 		2454
 2009-03-20 17:51:26 +00:00
Robert Noland
363fec5d16 Don't deref dev->dev_private before checking that it exists. 
Found with:	Coverity Prevent(tm)
CID:		2940

MFC after:	3 days
 2009-03-20 17:48:36 +00:00
Robert Noland
c20a7fc9f6 Only issue the wakeup and store the counter if vblank is enabled on 
the pipe.

MFC after:	3 days
 2009-03-20 04:53:12 +00:00
Robert Noland
c2dd8f68b0 Add a couple of radeon pci ids. 
MFC after:	3 days
 2009-03-20 04:49:48 +00:00
Robert Noland
9f85b82ccc Adjust the flags to bus_dmamem around here too. 
MFC after:	3 days
 2009-03-20 04:48:27 +00:00
Robert Noland
470fac3a17 Add some debugging so I can see when syscalls are being restarted 
consistantly.  After a lengthy irc discussion it seems like we
shouldn't need to worry about them, but it's nice to know about.

MFC after:	3 days
 2009-03-19 08:36:08 +00:00
Robert Noland
ea196ecaaa Rework vblank handling to try to resolve some reports of "slow" windows 
after vt switch or suspend.  I can't really test this on Intel right now
but I think I've heard reports of it on radeon as well.  I can't break
it on the radeon here.

MFC after:	3 days
 2009-03-19 08:34:04 +00:00
Robert Noland
324a23e9a2 Sync up the rest of the code that we use with what Intel is shipping 
-Some irq/vblank related changes that hopefully will help.
	-A little more cleanup while I'm here.

MFC after:	3 days
 2009-03-19 08:28:36 +00:00
Robert Noland
5a6ba2ffbc Pull in some suspend / resume changes from Intel's code 
Tested by:	mav@
MFC after:	3 days
 2009-03-19 08:22:56 +00:00
Robert Noland
b38c31bf40 Cast to (unsigned long) to make printf happy on i386 
MFC after:	3 days
 2009-03-17 05:10:12 +00:00
Robert Noland
c921ffc089 Add support for matching solely on vendor id. 
We will use this method with nouveau

MFC after:	3 days
 2009-03-17 03:53:44 +00:00
Robert Noland
f29130e3c2 Improve the debugging output of drm_mmap 
MFC after:	3 days
 2009-03-17 03:50:35 +00:00
Robert Noland
41a7f04fda Add list_for_each_prev to our linux compatibility. 
We need this for nouveau

MFC after:	3 days
 2009-03-17 03:49:24 +00:00
Robert Noland
a4501e547e Minor code cleanup 
MFC after:	3 days
 2009-03-17 03:46:37 +00:00
Robert Noland
d87f6722c5 We can have more than 3 pci resources 
MFC after:	3 days
 2009-03-17 03:44:36 +00:00
Robert Noland
ce3aaf8d2d Cast register maps and offsets to vm_offset_t 
MFC after:	3 days
 2009-03-17 03:39:09 +00:00
Robert Noland
b2a9095767 Change the logic around to match ati_pcigart. 
MFC after:	3 days
 2009-03-17 03:36:24 +00:00
Robert Noland
162e0ab8c1 Use flsl() here rather than ffsl() 
I discovered that we were computing page_order differently than linux.

MFC after:	3 days
 2009-03-17 03:32:12 +00:00
Robert Noland
6443904ee1 Use the right MSI_REARM for RS600. 
MFC after:	3 days
 2009-03-16 19:09:59 +00:00
Robert Noland
85c5cd4b94 Get rid of any remaining PZERO flags in mtx_sleep() 
Also, clean up some ifdef mess while I'm here.

MFC after:	3 days
 2009-03-16 08:19:11 +00:00
Robert Noland
96deaed545 Fix R600 writeback across suspend/resume. 
This is likely a NOOP for us, since I haven't ported the suspend/resume
code yet.

MFC after:	3 days
 2009-03-16 08:15:35 +00:00
Robert Noland
f0eb29f4a6 Consistently use kdev for the kernel device. 
Submitted by:	vehemens <vehemens@verizon.net>
MFC after:	3 days
 2009-03-09 07:55:18 +00:00
Robert Noland
4d4420bda8 Clean up the printing on amd64. Should also be consistent on i386. 
MFC after:	3 days
 2009-03-09 07:50:27 +00:00
Robert Noland
d3f8d87d33 There is no need to sync these buffers to swap. 
MFC after:	3 days
 2009-03-09 07:49:13 +00:00
Robert Noland
254c58f9fd Change the flags to bus_dmamem around to allow it to sleep waiting for 
resources during allocation, but not during map load.  Also, zero the
buffers here.

MFC after:	3 days
 2009-03-09 07:47:03 +00:00
Robert Noland
00a55e42d6 Fix the flags to bus_dmamem_* to allow the allocation to sleep while 
waiting for resources.  It is really the load that we can't defer.
BUS_DMA_NOCACHE belongs on bus_dmamap_load() as well.

MFC after:	3 days
 2009-03-09 07:38:22 +00:00
Robert Noland
bf32f93e11 -Make the PCI(E)/AGP calculations consistent 
-Calculate the scratch address correctly

MFC after:	10 days
 2009-03-09 07:33:35 +00:00
Robert Noland
566be5d4e1 Call the right function for the right chipset. 
MFC after:	10 days
 2009-03-09 07:24:32 +00:00
Robert Noland
4fcda8938e Import support for ATI Radeon R600 and R700 series chips. 
Tested on an HD3850 (RV670) on loan from Warren Block.

Currently, you need one of the following for this to be useful:

	x11-drivers/xf86-video-radeonhd-devel (not tested)
	xf86-video-ati from git (EXA works, xv is too fast)
	xf86-video-radeonhd from git (EXA works, xv works)

There is no 3d support available from dri just yet.

MFC after:	2 weeks
 2009-03-07 21:36:57 +00:00
Robert Noland
51e39089c9 Initialize the vblank structures at load time. Previously we did this 
at irq install/uninstall time, but when we vt switch, we uninstall the
irq handler.  When the irq handler is reinstalled, the modeset ioctl
happens first.  The modeset ioctl is supposed to tell us that we can
disable vblank interrupts if there are no active consumers.  This will
fail after a vt switch until another modeset ioctl is called via dpms
or xrandr.  Leading to cases where either interrupts are on and can't
be disabled, or worse, no interrupts at all.

MFC after:	2 weeks
 2009-02-28 02:37:55 +00:00
Robert Noland
45de2347c4 Add a tuneable to allow disabling msi on drm at runtime. 
Suggested by:	jhb@

MFC after:	2 weeks
 2009-02-27 23:50:55 +00:00
Robert Noland
2a4f4fc196 Fix up some ioctl permissions issues long overlooked. 
Submitted by:	jkim@
MFC after:	2 weeks
 2009-02-27 06:01:42 +00:00
Robert Noland
23b90efbcf The GM45 handles vblank differently. Pull the changes from Intel in. 
MFC after:	2 Weeks
 2009-02-25 20:24:13 +00:00
Robert Noland
cc27cbe330 Remove D_NEEDGIANT. 
MFC after:	2 weeks
 2009-02-25 18:56:49 +00:00
Robert Noland
bbc33a7d31 Turn on MSI if the card supports it. There is a blacklist for chips 
which report that they are capable of MSI, but don't work correctly.

MFC after:	2 weeks
 2009-02-25 18:54:35 +00:00
Robert Noland
5493c70e90 Prepare the radeon driver for MSI support. 
MFC after:	2 weeks
 2009-02-25 18:50:35 +00:00
Robert Noland
82369f9166 Add some vblank related debugging and replace the DRM_WAIT_ON macro 
with a localized version.

MFC after:	2 weeks
 2009-02-25 18:48:33 +00:00
Robert Noland
dc5c632deb This was part of a sync to the code that Intel is shipping in linux. 
- Remove the old TTM interface
	- Move register definitions to i915_reg.h
	- Overhaul the irq handler

MFC after:	2 weeks
 2009-02-25 18:44:50 +00:00
Robert Noland
67f435f03e The i915 driver was the only consumer of locked task support. 
Now that it doesn't use it anymore, get right of the taskqueue
and locked task support.

MFC after:	2 weeks
 2009-02-25 18:25:47 +00:00
Robert Noland
c148ca706e The vblank_swap ioctl was fundamentally race prone. Get rid of it. 
MFC after:	2 weeks
 2009-02-25 18:22:57 +00:00
Robert Noland
a87b4f7293 There is no reason to hold the lock here. 
When I was LOCK_PROFILING this was pretty high up and there is no
reason for it.

MFC after:	2 weeks
 2009-02-25 18:19:16 +00:00
Robert Noland
4f02999996 Remove the PZERO priority from mtx_sleep. 
MFC after:	2 weeks
 2009-02-25 18:16:50 +00:00
Robert Noland
b2dc68697e Only set registers if irqs are enabled 
Approved by:	kib
Obtained from:	drm git
 2008-12-23 22:53:57 +00:00
Robert Noland
241dd5673c Convert DRM_[DEBUG,ERROR,INFO] macros to c99 __VA_ARGS__. 
Approved by:	kib
 2008-12-21 22:32:01 +00:00
Robert Noland
73e1b34a9e Garbage collect entries from pcireg.h since we now include it. 
Approved by:	kib@
MFC after:	2 weeks
 2008-12-18 22:01:46 +00:00
Robert Noland
c9e7b21284 We only want drm to ever attach to the primary pci device. 
Intel 855 chips present the same pci id for both heads.  This prevents
us from attaching to the dummy second head.  All other chips that I
am aware of either only present a single pci id, or different ids
for each head so that we only match on the correct head.

Approved by:	kib@
MFC after:	2 weeks
 2008-12-18 21:58:57 +00:00
Robert Noland
8b8df0ff61 rework drm_scatter.c which allocates scatter / gather pages for use by 
ati pci gart to use bus_dma to handle the allocations.  This fixes
a garbled screen issue on at least some radeons (X1400 tested).  It is
also likely that this is the correct fix for PR# 119324, though that
is not confirmed yet.

Reviewed by:	jhb@ (mentor, prior version)
Approved by:	kib@
MFC after:	2 weeks
 2008-12-18 21:04:50 +00:00
Robert Noland
f3dcc5387b Fix error in busmaster enable logic 
rs400/rs480 should clear the RADEON_BUS_MASTER_DIS bit.  This should get
the rs485 IGP chips going again.

Approved by:	jhb (mentor)
Obtained from:	drm git master
 2008-10-27 21:24:34 +00:00