* Add an AR9340 switch version entry;
* Support the switch being connected via MII;
* Add a flag to note that a switch is actually an internal
switch rather than an external switch.
Now:
* The ar9340 switch can interconnect via MII;
* Since some slightly different phy/switch register access methods
and quirks appear for the internal versus external switch,
we will need a flag to mark it as an "internal" switch.
Tested:
* AR9344 (internal switch)
* AR9331 (internal switch)
TODO:
* Test the AR8316 switch!
This is just the chip initialisation code (for now.)
It's not linked into the main build as it requires a bunch of other code
to be tidied up and committed. But it indeed does function as advertised.
Tested:
* AR9344 SoC
arswitch_writereg() routine was writing the registers in the wrong order.
Revert -r241918 as the root problem is now fixed. Remove another workaround
from arswitch_ar7240.c.
Simplify and fix the code on arswitch_writephy() by using
arswitch_writereg().
While here remove a redundant declaration from arswitchvar.h.
Approved by: adrian (mentor)
This fix the case when etherswitch is printing the information of port 0
vlan group (in port based vlan mode) with no member ports.
Add the ETHERSWITCH_VID_VALID support to ip17x driver.
Add the ETHERSWITCH_VID_VALID support to rt8366 driver.
arswitch doesn't need to be updated as it doesn't support vlans management
yet.
Approved by: adrian (mentor)
* Fix API changes;
* remove unused code;
* Allow some switches to be used that don't expose a set of PHY
registers for the CPU facing port (eg the ADM6996 for the Ubiquiti
Routerstation.)
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by: ray
This adds a vlan capability field to etherswitch_info structure and some
definitions of ports flags.
It adds the support to global config parameters which right now is used
only to switch between the vlan modes, but it is intended to be extended
to support the setup of others parameters (STP, mirror, etc.).
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by: ray
than VLAN groups.
Some chips (eg this rtl8366rb) has a VLAN group per port - you first
define a set of VLANs in a vlan group, then you assign a VLAN group
to a port.
Other chips (eg the AR8xxx switch chips) have a VLAN ID array per
port - there's no group per se, just a list of vlans that can be
configured.
So for now, the switch API will use the latter and rely on drivers
doing the heavy lifting if one wishes to use the VLAN group method.
Maybe later on both can be supported.
PR: kern/177878
PR: kern/177873
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by: ray
This is intended to be used as a stop-gap for switch devices
which expose multiple ethernet PHYs but we don't have a driver
for - here, etherswitchcfg and the general switch configuration
API can be used to interface to said PHYs.
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
depending upon the bootloader initialising it.
The aim is to eventually support a full switch set and reinitialisation
rather than relying on a consistent bootloader setup.
Remove the port flood config from arswitch.c, it's not yet used and
it's totally incorrect.
Whilst I'm here, also add in a comment describing why the full switch
reset is disabled.
Obtained from: Linux (OpenWRT) - Values
size for the AR7240.
* Include SM/MS macros, thanks to ath_hal(4).
* This field is for normal packets, VLAN and other headers are added to
this by the switch device.
* Set the MTU to 1536, to match what is done in Linux. Use the SM
macro to write this field.
Obtained from: Atheros (AR7240 datasheet), Linux OpenWRT (MTU default)
* Add in the AR724x support. It probes the same as an AR8216/AR8316, so
just add in a hint to force the probe success rather than auto-detecting
it.
* Add in the missing entries from conf/files, lacking in the previous
commit.
The register values and CPU port / mirror port initialisation value was
obtained from Linux OpenWRT ag71xx_ar7240.c.
The DELAY(1000) to let things settle is my local workaround. For some
reason, PHY4 doesn't seem to probe very reliably without it. It's quite
possible that we're missing some MDIO bus initialisation code in if_arge
for the AR724x case. As I dislike DELAY() workarounds in general, it's
definitely worth trying to figure out why this is the case.
Tested on: AP93 (AR7240) reference design
Obtained from: Linux OpenWRT
This is designed to support the very basic ethernet switch chip behaviour,
specifically:
* accessing switch register space;
* accessing per-PHY registers (for switches that actually expose PHYs);
* basic vlan group support, which applies for the rtl8366 driver but not
for the atheros switches.
This also includes initial support for:
* rtl8366rb support - which is a 10/100/1000 switch which supports
vlan groups;
* Initial Atheros AR8316 switch support - which is a 10/100/1000 switch
which supports an alternate vlan configuration (so the vlan group
methods are stubbed.)
The general idea here is that the switch driver may speak to a variety of
backend busses (mdio, i2c, spi, whatever) and expose:
* If applicable, one or more MDIO busses which ethernet interfaces can
then attach PHYs to via miiproxy/mdioproxy;
* exposes miibusses, one for each port at the moment, so ..
* .. a PHY can be exposed on each miibus, for each switch port, with all
of the existing MII/ifnet framework.
However:
* The ifnet is manually created for now, and it isn't linked into the
interface list, nor can you (currently) send/receive frames on this ifnet.
At some point in the future there may be _some_ support for this, for
switches with a multi-port, isolated mode.
* I'm still in the process of sorting out correct(er) locking.
TODO:
* ray's switch code in zrouter (zrouter.org) includes a much more developed
newbus API that covers the various switch methods, as well as a
capability API so drivers, the switch layer and the userland utility
can properly control the subset of supported features.
The plan is to sort that out later, once the rest of ray's switch drivers
are brought over and extended to export MII busses and PHYs.
Submitted by: Stefan Bethke <stb@lassitu.de>
Reviewed by: ray
MDIO/MII rendezvous proxy.
* Add an 'mdio' bus, which is the "IO" side of an MII bus (but by design
can be anything which implements the underlying register access API.)
* Add 'miiproxy' and 'mdioproxy', which provides a rendezvous mechanism
for MII busses to appear hanging off arbitrary busses (ie, that aren't
necessarily a traditional looking MII bus.)
MII busses can now hang off anything that implements an mdiobus.
For the AR71xx SoC, there's one MDIO bus but two MII busses. So to
properly support two or more real PHYs, this can be done:
# arge0 MDIO bus - there's no arge1 MDIO bus for AR71xx
hint.argemdio.0.at="nexus0"
hint.argemdio.0.maddr=0x19000000
hint.argemdio.0.msize=0x1000
hint.argemdio.0.order=0
# Create two mdioproxy instances
hint.mdioproxy.0.at="mdio0"
hint.mdioproxy.1.at="mdio0"
# .. and with a follow-up patch
hint.arge.0.mdio=mdioproxy0
hint.arge.1.mdio=mdioproxy0
TODO:
* Do a sweep or two and add appropriate locking in mdio/mdioproxy/miiproxy.
Submitted by: Stefan Bethke <stb@lassitu.de>
Reviewed by: ray
