This avoids an immediate access bit fault when we serviced the dirty
bit fault in case the access bit is unset. This typically happens for
newly allocated memory that's being zeroed and thus very common.
which deals with both endianness and alignment issues.
- Collect low-hanging fruits for endianness safety.
- Use 0xffffffff instead of -1 where appropriate.
endian safe.
- Change some u_int to u_int8_t which make more sense here since
we're really defining bytes. That produces the same code due to
how bitfields work.
- Add the definition of the vlan_drop_en bit (not used yet).
- Add some useful comments.
Obtained from: NetBSD
RX part of this driver too. It's better since the code wasn't
dealing with bus_dmamap_load() returning EINPROGRESS, and this
can't happen with bus_dmamap_load_mbuf().
Submitted by: jake
other allocations/initializations have been successful. I kinda
doubt it will fix the recent breakage that some people are seeing,
but this could have caused problems for sure.
to take care of the KAME IPv6 code which needs ovbcopy() because NetBSD's
bcopy() doesn't handle overlap like ours.
Remove all implementations of ovbcopy().
Previously, bzero was a function pointer on i386, to save a jmp to
bzero_vector. Get rid of this microoptimization as it only confuses
things, adds machine-dependent code to an MD header, and doesn't really
save all that much.
This commit does not add my pagezero() / pagecopy() code.
Move the remaining bits of <sys/diskslice.h> to <i386/include/bootinfo.h>
Move i386/pc98 specific bits from <sys/reboot.h> to
<i386/include/bootinfo.h> as well.
Adjust includes in sys/boot accordingly.
actual address of buffer descriptor. This should fix the reported
calibration failures and subsequent speed problems with ich chipsets.
Minor calibration comment updates.
can do 64 bytes at a time and don't allocate lines in the L2 cache. These
assume that everything is 64 byte aligned, and that there's more than 128
bytes of data (best for whole pages). The block load and store instructions
don't follow normal memory ordering rules and require either a memory barrier
or move between registers before the data can actually be used. This
implementation correctly shuffles around 3 out of the 4 sets of registers
in order to avoid memory barriers expect for the last 2 blocks.
will be saved if we context switch as a result of an interrupt which occured
while using the floating point registers in the kernel (which actually can't
happen right now). This allows fp disabled traps in the kernel, which
normally shouldn't happen, so make sure the trapping code is what we expect
it is.
