Olivier Houchard
f60e923b23
- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32
...
interrupts.
- Implement teardown methods where appropriate.
2005-06-09 12:26:20 +00:00
Olivier Houchard
31d0686d2d
Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides
...
64 irqs.
This should be re-thought later.
2005-02-13 18:26:31 +00:00
Warner Losh
d8315c79d9
Start all license statements with /*-
2005-01-05 21:58:49 +00:00
Olivier Houchard
7c320e5bfb
Add new functions to know which irqs are pending, and to mask and unmask
...
interrupts, as these are CPU specific.
If the interrupt handler is not marked as INTR_FAST, don't unmask the
interrupt until it as been serviced.
2004-09-23 22:09:57 +00:00
Olivier Houchard
6fc729af63
Import FreeBSD/arm kernel bits.
...
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00