Use temporary filesystems / memory disks instead of a hardcoded path
which doesn't exist on test systems
MFC after: 2 weeks
Sponsored by: EMC / Isilon Storage Division
The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board
has an L2 cache:
Cache info:
picache_stride = 4096
picache_loopcount = 8
pdcache_stride = 4096
pdcache_loopcount = 8
cpu0: Ingenic Xburst processor v79.2
MMU: Standard TLB, 32 entries
L1 i-cache: 8 ways of 128 sets, 32 bytes per line
L1 d-cache: 8 ways of 128 sets, 32 bytes per line
L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size
Config1=0xbe67338b<WatchRegs,EJTAG,FPU>
Config2=0x80000267
Config3=0x20
match the physical load address. Remove the *PHYSADDR symbols which are no
longer necessary.
Also remove a bunch of comments, most of which which have been wrong for
quite some time now, and the rest of which are mooted by these changes. All
that's left in this file is assigning a single symbol to its cannonical
value, not much to comment on anymore.
This eliminates the reliance on PHYSADDR and KERNPHYSADDR compile-time
symbols (except when the rom-copy code is enabled) by using the current
PC and the assumption that the entry-point routine is in the first 1MB
section of the text segment.
Other cleanups done:
- Reduce the initarm() stack size back to 2K. It got increased to
4 * 2K when this file was supporting multicore armv6, but that
support is now in locore-v6.S.
- When building the temporary startup page tables, map the entire
4GB address space as VA=PA before mapping the kernel at its loaded
location. This allows access to boot parameters stored somewhere
in ram by the bootloader, regardless of where that may be.
- When building the page table entry for supporting EARLY_PRINTF, map
the section as uncached unbuffered, since it is presumably device
registers.
Note that this restores the ability to use loader(8)/ubldr on armv4/5
kernels. That was broken in r283035, the point at which ubldr started
loading an arm kernel at any 2MB boundary.
Also note that after this, there is no reason to set KERNVIRTADDR to
anything other than 0xc0000000, and no need for PHYSADDR or KERNPHYSADDR
symbols at all.
is what includes machine/ofw_machdep.h. Don't declare OF_decode_addr();
it isn't implemented yet on mips and the declaration for it is about to
be commonized into openfirm.h.
If ExitBootServices fails due to a changed efi_mapkey then GetMemoryMap
must be called again. In this case it is also possible for the memory
map to grow, so repeat the initial GetMemoryMap call to fetch the new
size.
Also roll bi_add_efi_data_and_exit into bi_load_efi_data as there's no
need for it to be a separate function.
PR: 202455
Reported by: Berislav Purgar <bpurgar@gmail.com>
Tested by: Berislav Purgar <bpurgar@gmail.com>
Reviewed by: kib
MFC after: 1 week
MFC with: r292338
Relnotes: Yes
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D4621
Depending on system configuration and parameters, clock_gettime() and
gettimeofday() may not be system calls. If so, passing an invalid pointer
will cause a signal and not an [EFAULT] error.
From a standards perspective, this is OK since passing an invalid pointer is
undefined behaviour.
MFC after: 1 week
Instead of using which(1) to look for doxygen, look for it in <LOCALBASE>/bin .
$PATH gets mangled by make buildenv, etc so it's better to just be explicit
about the path if someone uses that for instance.
Differential Revision: https://reviews.freebsd.org/D4406 (part of a larger diff)
Reviewed by: emaste, Evan Cramer <eccramer@gmail.com>
Sponsored by: EMC / Isilon Storage Division
Also, don't compile the ldexpl(3) testcases on platforms that don't support
the libcall (technically only x86 right now). This makes this test buildable on
arm*/mips*/powerpc*
PR: 205449 [*]
MFC after: 1 week
Tested on: stable/10 (amd64/i386), head (amd64/i386)
Sponsored by: EMC / Isilon Storage Division
It completely fails all assertions on i386 on both stable/9 and stable/10
PR: 205448
MFC after: 1 week
X-MFC to: stable/10
Sponsored by: EMC / Isilon Storage Division
- Use a separate variable for tracking the testcase count instead
of hardcoding the offset for the testcases
MFC after: 3 days
Sponsored by: EMC / Isilon Storage Division
Also, don't compile the exp2l(3) testcases on platforms that don't support the
libcall (technically only x86 right now). This makes this test buildable on
arm*/mips*/powerpc*
Tested on: stable/10 (amd64/i386), head (amd64/i386)
PR: 205446 [*]
MFC after: 1 week
X-MFC to: stable/10
Sponsored by: EMC / Isilon Storage Division
exhausted.
It is possible for a bug in the code (or, theoretically, even unusual
network conditions) to exhaust all possible mbufs or mbuf clusters.
When this occurs, things can grind to a halt fairly quickly. However,
we currently do not call mb_reclaim() unless the entire system is
experiencing a low-memory condition.
While it is best to try to prevent exhaustion of one of the mbuf zones,
it would also be useful to have a mechanism to attempt to recover from
these situations by freeing "expendable" mbufs.
This patch makes two changes:
a) The patch adds a generic API to the UMA zone allocator to set a
function that should be called when an allocation fails because the
zone limit has been reached. Because of the way this function can be
called, it really should do minimal work.
b) The patch uses this API to try to free mbufs when an allocation
fails from one of the mbuf zones because the zone limit has been
reached. The function schedules a callout to run mb_reclaim().
Differential Revision: https://reviews.freebsd.org/D3864
Reviewed by: gnn
Comments by: rrs, glebius
MFC after: 2 weeks
Sponsored by: Juniper Networks
Some applications (e.g. Kodi) use tvservice APIs to manage HDMI
modes, power state, EDID etc. directly through VideoCore. After
these manipulations VideoCore may loose its state and needs to be
resynced with ARM. Under Linux this problem is worked around using
fbset utility that recreates framebuffer. Since there is no fbset
utility in FreeBSD we provide sysctl for userland apps to get system
back into normal mode.
"The availability of CLWB instruction is indicated by the presence of
the CPUID feature flag CLWB (bit 24 of the EBX register)."
CLWB is similar to CLFLUSHOPT, except that it is not required to discard
cacheline contents.
"On processors that supports PCOMMIT, PCOMMIT is enumerated through
CPUID (CPUID.7.0.EBX[22]) only when the feature is enabled by BIOS."
PCOMMIT is used to cause store-to-memory operations to become persistent
(protected from power failure).
Sponsored by: EMC / Isilon Storage Division
