Commit Graph

4 Commits

Author SHA1 Message Date
Ruslan Bukin
3c8efd61f5 Revert r339421 due to unintended files included to commit.
Reported by:	ian
Approved by:	re (gjb)
Sponsored by:	DARPA, AFRL
2018-10-18 15:17:58 +00:00
Ruslan Bukin
53c6ad1d62 Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).

RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.

Reviewed by:	jhb, markj
Approved by:	re (gjb)
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D17424
2018-10-18 15:08:14 +00:00
Ruslan Bukin
05439eb571 Enable ARM PL330 DMA engine and Cadence Quad SPI flash controller on
Intel Arria 10 SoC boards.

Tested on Intel Arria 10 SoC Development Kit.

Sponsored by:	DARPA, AFRL
2018-04-23 12:23:05 +00:00
Warner Losh
2e36db147e Move sys/boot/fdt/dts to sys/dts and adjust scripts.
Sponsored by: Netflix
2017-11-14 21:03:57 +00:00