actually 16 I/O lines but the other ones are used for system devices and
interrupts.
The IXP4XX platform can set interrupts on these pins for
high/low/rising/falling/transitional but this is not implemented yet.
The Cambria has the same interface but as all the pins are assigned to system
functions the gpio header is toggled via a PLD on the i2c bus and is not
supported by this commit.
respectivly. This will allow one to have a kernel with both devices
present and use it for multiple boards with different types of RTC
sitting on a bus.
Discussed with: imp
o add bus shim for cfi driver
o add static mapping for CS0 (we map all 16M as the cfi driver doesn't
support demand mapping)
Note this needs some tweaking to work for 2358 boards which is why the
CAMBRIA config is not touched.
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
