reimplementations of enodev() (for the smbread() and smbwrite()
functions), as well as fixing various errno values to conform to
errno(3).
Bruce also points out that a number of the pointer == NULL tests
are probably nonsense because the respective checks are already
done at upper layers.
(Mostly) submitted by: bde
controllers and allows the controller to prefetch 1-2k on certain
PCI memory reads to the host. The spec says this should only be
used for IA32 based systems.
Informed of feature by: John Cagle <first.last@hp.com>
properly using copyin/copyout for more than 5 years? This one did. :-)
Properly encapsulate all user<->kernel data transfers using copy{in,out}.
MFC after: 1 month
NULL name in device_add_child(), explicitly name all of our known
child drivers in order to give them a chance to attach to us.
Otherwise, only the first one present would be probed and attached.
Reviewed by: nsouch
MFC after: 1 month
registers, so add a register offset array to the softc. We key off the
device ID to determine which set of register offsets. Currently the 8385
host bridge used on amd64 is the only bridge to use the AGP3_VIA_*
register offsets and all other bridges use the AGP_VIA_* offsets. It is
currently unclear if the AGP3_VIA_* offsets are for VIA bridges that
implement AGP 3.0 bridges or just for amd64 bridges.
Submitted by: Kenneth Culver culverk at sweetdreamsracing dot biz
proper locking to be checked at runtime.
Remove sb_lock() and sb_unlock() calls from sb_reset_dsp() because the
latter is called from sb_setup() with the lock already held. Add a
call to sb_lockassert().
Surround the call to sb_reset_dsp() in sb16_attach() with sb_lock()
and sb_unlock() calls.
Tested by: Bartek Marcinkiewicz <junior AT p233.if.pwr.wroc.pl>
Allow 500us between pauses in ahd_pause_and_flushwork().
The maximum we will wait is now 500ms.
In the same routine, remove any attempt to clear ENSELO.
Let the firmware do it once the current selection has
completed. This avoids some race conditions having to
do with non-packetized completions and the auto-clearing
of ENSELO on packetized completions.
Also avoid attempts to clear critical sections when
interrups are pending. We are going to loop again
anyway, so clearing critical sections is a waste of
time. It also may not be possible to clear a critical
section if the source of the interrupt was a SEQINT.
aic79xx_pci.c:
Use the Generic 9005 mask when looking for generic 7901B
parts. This allows the driver to attach to 7901B parts
on motherboards using a non-Adaptec subvendor ID.
aic79xx_inline.h:
Test for the SCBRAM_RD_BUG against the bugs
field, not the flags field in the softc.
aic79xx.c:
Cancel pending transactions on devices that
respond with a selection timeout. This decreases
the duration of timeout recovery when a device
disappears.
aic79xx.c:
Don't bother forcing renegotiation on a selection
timeout now that we use the device reset handler
to abort any pending commands on the target.
The device reset handler already takes us down
to async narrow and forces a renegotiation.
In the device reset handlers, only send a
BDR sent async event if the status is not
CAM_SEL_TIMEOUT. This avoids sending this
event in the selection timeout case
aic79xx.c:
Modify the Core timeout handler to verify that another
command has the potential to timeout before passing off
a command timeout as due to some other command. This
safety measure is added in response to a timeout recovery
failure on H2B where it appears that incoming reselection
status was lost during a drive pull test. In that case,
the recovery handler continued to wait for the command
that was active on the bus indefinetly. While the root
cause of the above issue is still being determined seems
a prudent safeguard.
aic79xx_pci.c:
Add a specific probe entry for the Dell OEM 39320(B).
aic79xx.c:
aic79xx.h:
aic79xx.reg:
aic79xx.seq:
Modify the aic79xx firmware to never cross a cacheline or
ADB boundary when DMA'ing completion entries to the host.
In PCI mode, at least in 32/33 configurations, the SCB
DMA engine may lose its place in the data-stream should
the target force a retry on something other than an
8byte aligned boundary. In PCI-X mode, we do this to
avoid split transactions since many chipsets seem to be
unable to format proper split completions to continue
the data transfer.
The above change allows us to drop our completion entries
from 8 bytes to 4. We were using 8 byte entries to ensure
that PCI retries could only occur on an 8byte aligned
boundary. Now that the sequencer guarantees this by splitting
up completions, we can safely drop the size to 4 bytes (2
byte tag, one byte SG_RESID, one byte pad).
Both the split-completion and PCI retry problems only show
up under high tag load when interrupt coalescing is being
especially effective. The switch from a 2byte completion
entry to an 8 byte entry to solve the PCI problem increased
the chance of incurring a split in PCI-X mode when multiple
transactions were completed at once. Dropping the completion
size to 4 bytes also means that we can complete more commands
in a single DMA (128byte FIFO -> 32 commands instead of 16).
aic79xx.c:
Modify the SCSIINT handler to defer clearing
sequencer critical sections to the individual
interrupt handlers. This allows us to
immediately disable any outgoing selections in
the case of an unexpected busfree so we don't
inadvertantly clear ENSELO *after* a new selection
has started. Doing so may cause the sequencer
to miss a successful selection.
In ahd_update_pending_scbs(), only clear ENSELO if
the bus is currently busy and a selection is not
already in progress or the sequencer has yet to
handle a pending selection. While we want to ensure
that the selection for the SCB at the head of the
selection queue is restarted so that any change in
negotiation request can take effect, we can't clobber
pending selection state without confusing the sequencer
into missing a selection.
sequencer interrupt codes. These codes are only
relevant to the code that was last being executed
and that context is cleared when we reset the
program counter. This addresses a race condition
between a sequencer interrupt and any SCSI event
that causes us to restart the sequencer.
o When running the untagged-Q, we must start the
timer for any transaction we queue.
o Give the firmware half a millisecond between
pauses to flush work out. This should give us
around half a second of total delay before flagging
an issue with pausing and flushing controller work.
Only attempt to clear critical sections if there
are no pending interrupts in the pause and flush
loop. If the sequencer has issued an INTSTAT, we
may not be able to step out of the critical section.
o Cancel pending transactions on devices that
respond with a selection timeout. This decreases
the duration of timeout recovery when a device
disappears.
Don't bother forcing renegotiation on a selection
timeout now that we use the device reset handler
to abort any pending commands on the target.
The device reset handler already takes us down
to async narrow and forces a renegotiation.
o In the device reset handlers, only send a
BDR sent async event if the status is not
CAM_SEL_TIMEOUT. This avoids sending this
event in the selection timeout case.
o Modify the Core timeout handler to verify that another
command has the potential to timeout before passing off
a command timeout as due to some other command.
the swizzle method for routing PCI interrupts across the bridge. This
fixes problems with motherboards (typically laptops) whose BIOS doesn't
provide a PRT for the AGP bridge even though there is a device entry for
the bridge in the ACPI namespace.
Tested by: Kenneth Culver culverk at sweetdreamsracing dot biz
there's not dependencies on pccard symboles, such a dependency is not
necessary. This means that drivers that have multiple attachments can
not drag bogus devices into the kernel at load time.
We can't (yet) do this with pci and isa. Drivers written for them
actually do seem to have symbols that depend on these busses'
implementation code.
ndis not touched until other things can be tested.
