mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)
Of these "partitions", only the enhanced user data area one actually
slices the user data area partition and, thus, gets handled with the
help of geom_flashmap(4). The other types of partitions have address
space independent from the default partition and need to be switched
to via CMD6 (SWITCH), i. e. constitute a set of additional "disks".
The second kind of these "partitions" doesn't fit that well into the
design of mmc(4) and mmcsd(4). I've decided to let mmcsd(4) hook all
of these "partitions" up as disk(9)'s (except for the RPMB partition
as it didn't seem to make much sense to be able to put a file-system
there and may require authentication; therefore, RPMB partitions are
solely accessible via the newly added IOCTL interface currently; see
also below). This approach for one resulted in cleaner code. Second,
it retains the notion of mmcsd(4) children corresponding to a single
physical device each. With the addition of some layering violations,
it also would have been possible for mmc(4) to add separate mmcsd(4)
instances with one disk each for all of these "partitions", however.
Still, both mmc(4) and mmcsd(4) share some common code now e. g. for
issuing CMD6, which has been factored out into mmc_subr.c.
Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.
CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.
- Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications. However, quite some work is
left to be done in this regard; all other R1B-type commands done by
the MMC layer also should be followed by a SEND_STATUS (CMD13), the
erase timeout calculations/handling as documented in specifications
are entirely ignored so far, the MMC layer doesn't provide timeouts
applicable up to the bridge drivers and at least sdhci(4) currently
is hardcoding 1 s as timeout for all command types unconditionally.
Let alone already available return codes often not being checked in
the MMC layer ...
- Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter will be added to ports as sysutils/mmc-utils in
a bit. Among others, the `mmc` tool of the GNU mmc-utils allows for
partitioning eMMC devices (tested working).
- For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.
- Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.
- In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
controllers as such in order to match the PCI one.
Additionally, in the entry for the 80860F14 SDXC controller remove
the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.
OKed by: imp
Submitted by: ian (mmc_switch_status() implementation)
as kernel drivers and their dependency onto mmc(4); this allows for
incrementing the mmc(4) module version but also for entire omission
of these bridge declarations for mmccam(4) in a single place, i. e.
in dev/mmc/bridge.h.
comments, marking unused parameters as such, style(9), whitespace,
etc.
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method (I've whipped these out of the tree as part of r227843
once, but they keep coming back ...),
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.
o Trim/adjust includes.
Replace archaic "busses" with modern form "buses."
Intentionally excluded:
* Old/random drivers I didn't recognize
* Old hardware in general
* Use of "busses" in code as identifiers
No functional change.
http://grammarist.com/spelling/buses-busses/
PR: 216099
Reported by: bltsrc at mail.ru
Sponsored by: Dell EMC Isilon
or write, resulting in random short-read and short-write returns for
requests. Fixing this fixes nominal block I/O via mmcsd(4).
Obtained from: DragonFlyBSD (fd4b97583be1a1e57234713c25f6e81bc0411cb0)
MFC after: 5 days
And HP x2 210, per DragonFlyBSD 240bd9cd58f8259c12c14a8006837e698.
Submitted by: Johannes Lundberg <yohanesu75 at gmail.com>
No objection: gonzo@
Obtained from: DragonFlyBSD
a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This
is because the kernel linker only searches for symbols in dependent modules,
so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc
was not compiled into the kernel (even if you hand-loaded mmc first).
(Thanks to jilles@ for providing the vital clue about the kernel linker.)
for all struct bio you get back from g_{new,alloc}_bio. Temporary
bios that you create on the stack or elsewhere should use this before
first use of the bio, and between uses of the bio. At the moment, it
is nothing more than a wrapper around bzero, but that may change in
the future. The wrapper also removes one place where we encode the
size of struct bio in the KBI.
SoC is used in the HiKey board from 96boards.
Currently on the SD card is working on the HiKey, as such devices 0 and 2
will need to be disabled, for example by adding the following to
loader.conf:
hint.hisi_dwmmc.0.disabled=1
hint.hisi_dwmmc.2.disabled=1
Relnotes: yes (Hikey board booting)
Sponsored by: ABT Systems Ltd
with some cards that causes them to become deselected after probing for
switch capabilities. The old workaround fixes the behavior with some cards,
but causes problems with the cards the behave correctly and don't become
deselected. Forcing a deselect then reselect appears to work correctly
with all cards in initial testing.
tend to be invalid. On a Beaglebone Black, we get 8192 sectors per
track and that causes major breakages.
Differential Revision: D2646
Reviewed by: ian@ imp@
This is based on the patch sent by Alexander Fedorov with the following
fixes/improvements:
- Better error handling;
- Clock is derived from PLL6 (obtained from netbsd);
- No more unnecessary busy loops on interrupt handler;
- style(9) fixes and code cleanup.
I also want to thanks Martin Galvan who has sent an alternative
implementation with some interesting fixes.
Tested on CubieBoard2, Banana-Pi (thanks to netgate!) and Cubieboard1
(Pratik Singhal).
This is intended to pave the way for the upcoming GSoC work (and make
easier the build of images for the supported boards).
PR: 196081
Submitted by: Alexander Fedorov <alexander.fedorov@rtlservice.com>
boards, this prevents some error messages during enumeration and also
gives us the correct erase block size. They appear to be harmless
elsewhere.
# Note: we treat too many commands as 'can't fail' if they don't work
# after a couple of retries. We need to fix that, but not today...
specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.
The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer
Submitted by: John Wehle
Approved by: stas (mentor)
Summary:
For new eMMC chips, we must signal controller HC capability in OP_COND command.
Reviewers: imp, ian
Reviewed By: ian
Differential Revision: https://reviews.freebsd.org/D1920
driver on Rockchip boards. It currently supports PIO mode
and dma mode needs external dma controller to be used.
Submitted by: jmcneill
Approved by: stas (mentor)
deselect it after setting the block size. This is a similar bug that
was fixed elsewhere, but not here. This makes sure that we leave the
card deselected at the end of the loop, and we don't send any commands
to the card without it selected.
Reviewed by: ian@
such as timeouts while probing a bus or testing for a feature, is
squelched. Also, error reporting is limited to 5 events per second,
because when an sdcard goes bad on a low-end embedded board, flooding
the console at high speed isn't helpful.
Original logging code contributed by Michal Meloun, but then I fancied
it up with squelching and ppsratecheck.
function parameters, the card has to be in transfer state. If it is in
the idle state, the commands are ignored. This caused us not to set
the proper parameters that we later assume to be present, leading to
downstream failures of the card / interface as our state machine
mismatches the card's.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>, Michal Meloun
<meloun at miracle.cz>
used to align partitions in gpart. We also try to align partitions by
stripe size when creating new media. Align these two concepts by
making fwsectors the same as the stripe size. Select a sensible number
of heads so we wind up with about 20 cylinders. This number was
selected to keep the rounding effects to a few percent while keeping
the number of cylinder groups low.
Sadly, it is not possible to make these numbers match the numbers used
by SD card readers. There apperas to be much variation between brands
so there's no one universal number. These numbers are also not aligned
to the stripe size, so some performance problems may still be present
when SD cards are created this way.
Also, these numbers will differ from the far less common SD to ATA
adapters, which present a different, but more uniform, set of numbers
that also happened to match the old defaults.
Nothing should change for current users. Any suboptimal performance
caused by misalignment will still be there. gpart will honor the
partitions that aren't on proper boudnaries, but editing the partition
tables may result in different alignments being used than before when
editing things natively.
Ideally, there'd be some way to override these values in the disk
subsystem by the user for the USB adapter use case where all "native"
notions of geometry disappear. This does not implement that.
In the mmcsd layer use this value to populate disk->d_ident. Also set
disk->d_descr to the full set of card identification info (includes vendor,
model, manufacturing date, etc).
