It seems generation of link state change of e1000phy(4) is not
reliable on some Marvell PHYs. If msk(4) know it still does not
have established link check whether msk(4) missed the link state
change by looking into polled link state.
Reported by: Mel Flynn < mel.flynn+fbsd.current <> mailing.thruhere dot net >,
Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
Tested by: Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
r198996:
Remove unnecessary header file.
r198997:
It's normal to see Rx FIFO overruns under high network load and
showing the message creates other side-effects. Remove the Rx
FIFO overrun message in interrupt handler. msk(4) should recover
from the FIFO overruns without any user intervention. Users can
still check the Rx FIFO overrun counter from MAC MIB statistics
maintained in driver(dev.msk.0.stats.rx.overflows).
Add a check to know whether driver is still running after
reacquiring driver lock in Rx handler. re(4) drops a driver lock
before passing received frame to upper stack and reacquire the
lock. During the time window ioctl calls could be executed and if
the ioctl was interface down request, driver will stop the
controller and free allocated mbufs. After that when driver comes
back to Rx handler again it does not know what was happend so it
could access free mbufs which in turn cause panic.
Reported by: Norbert Papke < npapk <> acm dot org >
Tested by: Norbert Papke < npapk <> acm dot org >
For AR8132 fast ethernet controller, do not report 1000baseT
capability to mii(4). Even though AR8132 uses the same model/
revision number of F1 gigabit PHY, the PHY has no ability to
establish 1000baseT link. I have no idea why Atheros use the same
device/model id for this PHY.
With this change atphy(4) does not report 1000baseT media
capability and manual 1000baseT configuration is also disabled
which is more desirable behavior for 10/100Mbps PHY.
Add DGE-560SX(Yukon XL) to the supported device list. Many thanks
to "Eugene Perevyazko <john <> dnepro dot net>" who kindly gave
remote access to system with DGE-560SX.
Add hack to pass controller specific information to phy driver.
Unlike most other PHYs there is no easy way to know which media
type the PHY supports on Marvell PHYs. MIIF_HAVEFIBER flags is now
passed via bus-specific instance variable of a device. While I'm
here add 88E1112 specific work around to set SIGDET polarity low.
Many thanks "Eugene Perevyazko <john <> dnepro dot net>" who kindly
gave remote access to system with DGE-560SX.
Provide a real fix to the too-many-translations problem when booting
from CD on 64-bit hardware to replace existing band-aids. This occurred
when the preloaded mdroot required too many mappings for the static
buffer.
Since we only use the translations buffer once, allocate a dynamic
buffer on the stack. This early in the boot process, the call chain
is quite short and we can be assured of having sufficient stack space.
SMP support for PowerPC G5 systems.
r198724:
Fix a race in casuword() exposed by csup. casuword() non-atomically
read the current value of its argument before atomically replacing it,
which could occasionally return the wrong value on an SMP system. This
resulted in user mutex operations hanging when using threaded applications.
r198723,198725,198731:
Loop on blocked threads when using ULE scheduler, removing an
XXX MP comment.
r198427:
Add some more paranoia to setting HID registers, and update the AIM
clock routines to work better with SMP.
r198378:
Add SMP support on U3-based G5 systems. While here, correct the
64-bit tlbie function to set the CPU to 64-bit mode correctly.
r198212:
Don't assume that physical addresses are identity mapped. This
allows the second processor on G5 systems to start.
Do not map the trap vectors into the kernel's address space. They are
only used in real mode and keeping them mapped only serves to make NULL
a valid address, which results in silent NULL pointer deferences.
Suggested by: Patrick Kerharo
Obtained from: projects/ppc64
Add sysctls in ahd(4) in order to keep track of different classes of
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.
Sponsored by: Sandvine Incorporated
Add the possibility for vfs.root.mountfrom tunable to accept a list of
items rather than a single one.
While there fix also a nit in a comment.
Sponsored by: Sandvine Incorporated
Provide an effective (relocated) address when building modules metadata.
This lets modules loaded dynamically in loader(8) work for U-Boot-based
platforms.
- U-Boot support library for loader(8) (ARM, PowerPC)
- multiprocessor (SMP) (PowerPC)
- E500 (Book-E) embedded CPU support (PowerPC)
- Freescale PowerQUICCIII MPC85xx system-on-chip support (single-
and dual-core) (PowerPC)
- Feroceon, Sheeva embedded CPU support
- Marvell Orion (88F5281), Kirkwood (88F6281) and Discovery
Innovation (MV-78100) systems-on-chip support (ARM)
- DS133x and DS1553 RTC support
- tsec(4) Gigabit Ethernet driver
- mge(4) Gigabit Ethernet driver
- kernel core dump support (PowerPC)
- mini dump support (ARM)
- gdbserver(1) support for (ARM, PowerPC)
Submitted by: raj
Fix parsing of mount options specified with -o in case an option with
value is preceded by an option without value (for example -o
option1,option2=value). Options must be separated before searching for
'='. Also compare pnextopt explicitly against NULL.
PR: bin/134069
Approved by: trasz (mentor)
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU
core, only pair of them. As result, both cores are running on highest
one of requested frequencies, and that is reported by status register.
Such behavior confuses frequency validation logic, as it runs on only
one core, as SMP is not yet launched, making EIST completely unusable.
Disable frequency validation by default, for systems with more then one
CPU, until we can implement it properly. It looks like making more harm
now then benefits. Add 'hw.est.strict' loader tunable to control it.
PR: amd64/140506
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.
Use only lower byte of sectors_intr IDENTIFY word as sector count.
This fixes SET_MULTI error during boot on devices supporting less then
16 sectors per interrupt.
Do not attach JMicrons with single PCI function. They are not working as
AHCI for some reason, even when declaring so. Let atajmicron configure
them for us and provide PATA support.
Correct the information about the doceng@ team members - Murray Stokely
stepped down some time ago, about the same time as Giorgos Keramidas
joined the team.
PR: 140465
Submitted by: Denny Lin <dennylin93@cnmc32.hs.ntnu.edu.tw>
